MMCCMB2107 Freescale, MMCCMB2107 Datasheet - Page 145

• Manufacturer Part Number: MMCCMB2107
• Manufacturer: Freescale

Specifications of MMCCMB2107

• Lead Free Status / RoHS Status: Not Compliant

6.4 Microarchitecture Summary
MMC2107 – Rev. 2.0
MOTOROLA
DATA CALCULATION
WRITEBACK BUS
SIGN EXT.
GENERAL-PURPOSE
REGISTER FILE
X PORT
32 BITS X 16
ADDER/LOGICAL PRIORITY ENCODER/
MUX
ZERO DETECT RESULT MUX
BARREL SHIFTER
REGISTER FILE
Figure 6-1. M•CORE Processor Block Diagram
ALTERNATE
32 BITS X 16
MULTIPLIER
Figure 6-1
The processor utilizes a 4-stage pipeline for instruction execution. The
instruction fetch, instruction decode/register file read, execute, and
register file writeback stages operate in an overlapped fashion, allowing
single clock instruction execution for most instructions.
The execution unit consists of a 32-bit arithmetic/logic unit, a 32-bit
barrel shifter, a find-first-one unit, result feed-forward hardware, and
miscellaneous support hardware for multiplication, division, and
multiple-register loads and stores.
DIVIDER
Freescale Semiconductor, Inc.
M•CORE M210 Central Processor Unit (CPU)
For More Information On This Product,
H/W ACCELERATOR INTERFACE BUS
Y PORT
MUX
is a block diagram of the M•CORE processor.
REGISTER FILE
Go to: www.freescale.com
SCALE
32 BITS X 13
CONTROL
IMMEDIATE
MUX
DATA
BUS
M•CORE M210 Central Processor Unit (CPU)
INCREMENT
ADDRESS GENERATION
INSTRUCTION PIPELINE
INSTRUCTION DECODE
PC
ADDRESS MUX
Microarchitecture Summary
BRANCH
ADDER
Technical Data
ADDRESS
BUS
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