MMCCMB2107 Freescale, MMCCMB2107 Datasheet - Page 576

• Manufacturer Part Number: MMCCMB2107
• Manufacturer: Freescale

Specifications of MMCCMB2107

• Lead Free Status / RoHS Status: Not Compliant

JTAG Test Access Port and OnCE
21.14.11 Enabling OnCE Memory Breakpoints
21.14.12 Pipeline Information and Write-Back Bus Register
Technical Data
576
When the OnCE memory breakpoint mechanism is enabled with a
breakpoint counter value of zero, the device enters debug mode after
completing the execution of the instruction that caused the memory
breakpoint to occur. In case of breakpoints on instruction fetches, the
breakpoint is acknowledged immediately after the execution of the
fetched instruction. In case of breakpoints on data memory addresses,
the breakpoint is acknowledged after the completion of the memory
access instruction.
A number of on-chip registers store the CPU pipeline status and are
configured in the CPU scan chain register (CPUSCR) for access by the
OnCE controller. The CPUSCR is used to restore the pipeline and
resume normal device activity upon return from debug mode. The
CPUSCR also provides a mechanism for the emulator software to
access processor and memory contents.
diagram of the pipeline information registers contained in the CPUSCR.
Freescale Semiconductor, Inc.
For More Information On This Product,
TDI
Figure 21-13. CPU Scan Chain Register (CPUSCR)
JTAG Test Access Port and OnCE
Go to: www.freescale.com
15
31
31
31
CTL
0
WBBR
PSR
PC
15
Figure 21-13
IR
MMC2107 – Rev. 2.0
0
0
0
shows the block
0
TDO
MOTOROLA