MMCCMB2107 Freescale, MMCCMB2107 Datasheet - Page 477

• Manufacturer Part Number: MMCCMB2107
• Manufacturer: Freescale

Specifications of MMCCMB2107

• Lead Free Status / RoHS Status: Not Compliant

MMC2107 – Rev. 2.0
MOTOROLA
QUEUE1 AND QUEUE2 TIMER
LOW-TIME
CYCLES (PSL) [3]
MODE RATE SELECTION [8]
CYCLES (PSH) [5]
INPUT SAMPLE TIME
SYSTEM CLOCK (f
FROM CCW [2]
HIGH-TIME
Figure 18-42. QADC Clock Subsystem Functions
sys
)
To accommodate wide variations of the main MCU clock frequency
(IPbus system clock – f
prescaler which divides the MCU system clock. To allow the A/D
conversion time to be maximized across the spectrum of system clock
frequencies, the QADC prescaler permits the frequency of QCLK to be
software selectable. It also allows the duty cycle of the QCLK waveform
to be programmable.
The software establishes the basic high phase of the QCLK waveform
with the PSH (prescaler clock high time) field in QACR0 and selects the
basic low phase of QCLK with the PSL (prescaler clock low time) field.
The combination of the PSH and PSL parameters establishes the
frequency of the QCLK.
Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
27 28 29 210 211 212 213 214 215 216 217
DOWN COUNTER
DETECT
ONE’S COMPLEMENT
PERIODIC TIMER/INTERVAL TIMER
ZERO
5-BIT
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[5]
BINARY COUNTER
ATD CONVERTER
STATE MACHINE
[3]
SELECT
sys
LOAD PSH
), QCLK is generated by a programmable
SET QCLK
Queued Analog-to-Digital Converter (QADC)
GENERATE
CLOCK
PERIODIC/INTERVAL TRIGGER
EVENT FOR Q1 AND Q2 [2]
SAR CONTROL
SAR [10]
QCLK
f
sys
/2 to f
sys
Technical Data
/40
Digital Control
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