MMCCMB2107 Freescale, MMCCMB2107 Datasheet - Page 416

• Manufacturer Part Number: MMCCMB2107
• Manufacturer: Freescale

Specifications of MMCCMB2107

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Queued Analog-to-Digital Converter (QADC)
18.8.5 Control Registers
18.8.5.1 Control Register 0
Technical Data
416
Address: 0x00ca_000a and 0x00ca_000b
Reset:
Reset:
Read:
Read:
Write:
Write:
This subsection describes the QADC control registers.
Control register 0 (QACR0) establishes the QCLK with prescaler
parameter fields and defines whether external multiplexing is enabled.
They are typically written once when the software initializes the QADC
and not changed afterward.
Read: Anytime
Write: Anytime except stop mode
MUX — Externally Multiplexed Mode Bit
The MUX bit allows the software to select the externally multiplexed
mode, which affects the interpretation of the channel numbers and
forces the MA[1:0] pins to be outputs.
Freescale Semiconductor, Inc.
Figure 18-8. QADC Control Register 0 (QACR0)
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
1 = Externally multiplexed, 18 possible channels
0 = Internally multiplexed, eight possible channels
Bit 15
PSH7
MUX
Bit 7
0
0
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= Writes have no effect and the access terminates without a transfer error exception.
PSH6
14
0
0
6
0
PSH5
13
0
0
5
1
PSH4
TRG
12
0
4
1
PSA
11
0
0
3
0
PSL2
10
0
0
2
1
MMC2107 – Rev. 2.0
PSL1
9
0
0
1
1
MOTOROLA
PSH8
PSL0
Bit 8
Bit 0
0
1