MMCCMB2107 Freescale, MMCCMB2107 Datasheet
MMCCMB2107
Specifications of MMCCMB2107
MMCCMB2107 Summary of contents
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MMC2107/D REV 2 MMC2107 Technical Data HCMOS Microcontroller Unit ...
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... Freescale Semiconductor, Inc. blank For More Information On This Product, Go to: www.freescale.com ...
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... Motorola was negligent regarding the design or manufacture of the part. Motorola, Inc Equal Opportunity/Affirmative Action Employer. Motorola and are registered trademarks of Motorola, Inc. DigitalDNA is a trademark of Motorola, Inc. MMC2107 – Rev. 2.0 MOTOROLA For More Information On This Product, Go to: www.freescale.com © Motorola, Inc., 2000 Technical Data 3 ...
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... Freescale Semiconductor, Inc. Technical Data Technical Data 4 For More Information On This Product, Go to: www.freescale.com MMC2107 – Rev. 2.0 MOTOROLA ...
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... Section 14. Programmable Interrupt Timer Section 15. Timer Modules (TIM1 and TIM2 293 MMC2107 – Rev. 2.0 MOTOROLA For More Information On This Product, Unit (CPU 143 (SRAM 175 (CMFR 179 Modules (PIT1 and PIT2 281 List of Sections Go to: www.freescale.com List of Sections Technical Data 5 ...
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... Section 21. JTAG Test Access Port and OnCE . . . . . . 533 Section 22. Electrical Specifications 585 Section 23. Mechanical Specifications . . . . . . . . . . . . . 609 Section 24. Ordering Information . . . . . . . . . . . . . . . . . 615 Technical Data 6 Modules (SCI1 and SCI2 329 Module (SPI 371 Converter (QADC 399 List of Sections For More Information On This Product, Go to: www.freescale.com MMC2107 – Rev. 2.0 MOTOROLA ...
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... Section 2. System Memory Map Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Address Map Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Section 3. Chip Configuration Module (CCM) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Single-Chip Mode Emulation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 Factory Access Slave Test (FAST) Mode . . . . . . . . . . . . . . 91 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 Table of Contents Go to: www.freescale.com Table of Contents Technical Data 7 ...
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... Reset Out (RSTOUT 121 Phase-Lock Loop (PLL) and Clock Signals . . . . . . . . . . . . 122 External Clock In (EXTAL .122 Crystal (XTAL 122 Clock Out (CLKOUT 122 Synthesizer Power (V DDSYN Table of Contents For More Information On This Product, Go to: www.freescale.com and 122 SSSYN MMC2107 – Rev. 2.0 MOTOROLA ...
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... Debug and Emulation Support Signals . . . . . . . . . . . . . . . 127 Test Reset (TRST 127 Test Clock (TCLK 127 Test Mode Select (TMS 127 Test Data Input (TDI 127 Test Data Output (TDO 127 Debug Event (DE 127 Table of Contents Go to: www.freescale.com Table of Contents ) . . . . . . . . . . . . . . . . . 126 .126 SSA Technical Data 9 ...
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... Reset Control Flow 138 Synchronous Reset Requests . . . . . . . . . . . . . . . . . . . . 138 Internal Reset Request . . . . . . . . . . . . . . . . . . . . . . . . . 140 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Concurrent Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Reset Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Reset Status Flags 141 Interrupts 141 Table of Contents For More Information On This Product, Go to: www.freescale.com ) . . . . . . . . . . . . 128 128 MMC2107 – Rev. 2.0 MOTOROLA ...
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... Fast Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . 165 Fast Interrupt Pending Register . . . . . . . . . . . . . . . . . . .166 Priority Level Select Registers . . . . . . . . . . . . . . . . . . . . 167 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Interrupt Sources and Prioritization . . . . . . . . . . . . . . . . . .168 Fast and Normal Interrupt Requests . . . . . . . . . . . . . . . . . 168 Autovectored and Vectored Interrupt Requests . . . . . . . . .169 Table of Contents Go to: www.freescale.com Table of Contents Technical Data 11 ...
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... CMFR Module Configuration Register . . . . . . . . . . . . . .188 CMFR Module Test Register . . . . . . . . . . . . . . . . . . . . . 193 CMFR High-Voltage Control Register . . . . . . . . . . . . . . 196 Array Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203 Read Page Buffers 203 Program Page Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . 204 Table of Contents For More Information On This Product, Go to: www.freescale.com ) . . . . . . . . . . . . . . . . . . . . 176 STBY MMC2107 – Rev. 2.0 MOTOROLA ...
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... Normal PLL Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 1:1 PLL Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 External Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 Wait and Doze Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 223 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225 EXTAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 XTAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 CLKOUT 225 Table of Contents Go to: www.freescale.com Table of Contents Technical Data 13 ...
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... Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 249 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 Port Output Data Registers . . . . . . . . . . . . . . . . . . . . . . 251 Port Data Direction Registers 252 Table of Contents For More Information On This Product, Go to: www.freescale.com MMC2107 – Rev. 2.0 MOTOROLA ...
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... Edge Port Pin Data Register . . . . . . . . . . . . . . . . . . . . . 268 Edge Port Flag Register 269 Section 13. Watchdog Timer Module Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .272 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .272 Doze Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .272 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .272 Debug Mode 272 Table of Contents Go to: www.freescale.com Table of Contents Technical Data 15 ...
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... PIT Control and Status Register . . . . . . . . . . . . . . . . . .285 PIT Modulus Register . . . . . . . . . . . . . . . . . . . . . . . . . . 288 PIT Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 Set-and-Forget Timer Operation . . . . . . . . . . . . . . . . . . . . 290 Free-Running Timer Operation . . . . . . . . . . . . . . . . . . . . . 291 Timeout Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . .291 Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 Table of Contents For More Information On This Product, Go to: www.freescale.com MMC2107 – Rev. 2.0 MOTOROLA ...
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... Timer Output Compare 3 Mask Register . . . . . . . . . . . . . . 302 Timer Output Compare 3 Data Register 303 Timer Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 304 Timer System Control Register 305 Timer Toggle-On-Overflow Register . . . . . . . . . . . . . . . . . 306 Timer Control Register 307 Timer Control Register 308 Table of Contents Go to: www.freescale.com Table of Contents Technical Data 17 ...
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... SCI Control Register .337 SCI Control Register .340 SCI Status Register 342 SCI Status Register 344 SCI Data Registers 345 SCI Pullup and Reduced Drive Register . . . . . . . . . . . . . . 346 Table of Contents For More Information On This Product, Go to: www.freescale.com MMC2107 – Rev. 2.0 MOTOROLA ...
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... SCI Port Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .347 SCI Data Direction Register . . . . . . . . . . . . . . . . . . . . . . . . 348 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 Slow Data Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 Fast Data Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . 364 Idle Input Line Wakeup (WAKE = 365 Address Mark Wakeup (WAKE = 1 365 Table of Contents Go to: www.freescale.com Table of Contents Technical Data 19 ...
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... Bidirectional Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .395 Write Collision Error . . . . . . . . . . . . . . . . . . . . . . . . . . . .395 Mode Fault Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 Low-Power Mode Options . . . . . . . . . . . . . . . . . . . . . . . . . 396 Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396 Doze Mode 396 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396 Table of Contents For More Information On This Product, Go to: www.freescale.com MMC2107 – Rev. 2.0 MOTOROLA ...
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... Voltage Reference Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 409 Dedicated Analog Supply Pins . . . . . . . . . . . . . . . . . . . . . . 409 Memory Map 409 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 QADC Module Configuration Register . . . . . . . . . . . . . . . . 411 QADC Test Register 412 Port Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 Port QA Data Direction Register . . . . . . . . . . . . . . . . . . . . 414 Table of Contents Go to: www.freescale.com Table of Contents Technical Data 21 ...
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... Channel Decode and Multiplexer . . . . . . . . . . . . . . . . . . 448 Sample Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .448 Digital-to-Analog Converter (DAC) Array . . . . . . . . . . . . 449 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449 Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449 Successive-Approximation Register . . . . . . . . . . . . . . . 449 State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .450 Queue Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .451 Queue Priority Schemes . . . . . . . . . . . . . . . . . . . . . . . . 453 Table of Contents For More Information On This Product, Go to: www.freescale.com MMC2107 – Rev. 2.0 MOTOROLA ...
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... Error Resulting from Leakage . . . . . . . . . . . . . . . . . . . . 499 Section 19. External Bus Interface Module (EBI) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .505 Data Bus (D[31:0 506 Show Cycle Strobe (SHS 506 Transfer Acknowledge (TA 506 Transfer Error Acknowledge (TEA .506 Table of Contents Go to: www.freescale.com Table of Contents Technical Data 23 ...
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... Emulation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516 Emulation Chip-Selects (CSE[1:0 .516 Internal Data Transfer Display (Show Cycles 517 Show Strobe (SHS 518 Section 20. Chip Select Module Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522 Table of Contents For More Information On This Product, Go to: www.freescale.com MMC2107 – Rev. 2.0 MOTOROLA ...
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... EXTEST Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541 IDCODE Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542 SAMPLE/PRELOAD Instruction . . . . . . . . . . . . . . . . . . . . . 543 ENABLE_MCU_ONCE Instruction . . . . . . . . . . . . . . . . . . .543 HIGHZ Instruction 544 CLAMP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544 BYPASS Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544 IDCODE Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545 Bypass Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546 Boundary SCAN Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .546 Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546 Table of Contents Go to: www.freescale.com Table of Contents Technical Data 25 ...
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... Trace Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574 Debug Request During RESET . . . . . . . . . . . . . . . . . . .574 Debug Request During Normal Activity . . . . . . . . . . . . . 575 Debug Request During Stop, Doze, or Wait Mode . . . .575 Software Request During Normal Activity . . . . . . . . . . . 575 Table of Contents For More Information On This Product, Go to: www.freescale.com MMC2107 – Rev. 2.0 MOTOROLA ...
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... Section 22. Electrical Specifications Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 586 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587 Electrostatic Discharge (ESD) Protection . . . . . . . . . . . . . . . . 587 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 588 PLL Electrical Specifications 590 QADC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . .591 Table of Contents Go to: www.freescale.com Table of Contents Technical Data 27 ...
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... Package Information for the 100-Pin LQFP . . . . . . . . . . . . . . 611 144-Pin LQFP Mechanical Drawing . . . . . . . . . . . . . . . . . . . . 612 100-Pin LQFP Mechanical Drawing . . . . . . . . . . . . . . . . . . . . 613 Section 24. Ordering Information Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .615 Table of Contents For More Information On This Product, Go to: www.freescale.com MMC2107 – Rev. 2.0 MOTOROLA ...
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... Data Organization in Memory .149 Data Organization in Registers . . . . . . . . . . . . . . . . . . . . . 149 Interrupt Controller Block Diagram . . . . . . . . . . . . . . . . . . .155 Interrupt Control Register (ICR 157 Interrupt Status Register (ISR 159 Interrupt Force Register High (IFRH 160 Interrupt Force Register Low (IFRL 161 List of Figures Go to: www.freescale.com List of Figures Page Technical Data 29 ...
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... Port Pin Data/Set Data Registers (PORTxP/SETx 253 Port Clear Output Data Registers (CLRx 254 Port C, D, I7, and I6 Pin Assignment Register (PCDPAR .255 Port E Pin Assignment Register (PEPAR 256 List of Figures For More Information On This Product, Go to: www.freescale.com Page MMC2107 – Rev. 2.0 MOTOROLA ...
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... Timer Counter Register High (TIMCNTH 304 Timer Counter Register Low (TIMCNTL .304 Timer System Control Register (TIMSCR1 305 Fast Clear Flag Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 Timer Toggle-On-Overflow Register (TIMTOV .306 Timer Control Register 1 (TIMCTL1 307 List of Figures Go to: www.freescale.com List of Figures Page Technical Data 31 ...
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... SCI Data Formats 349 Transmitter Block Diagram 351 SCI Receiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . .356 Receiver Data Sampling 357 Start Bit Search Example 359 Start Bit Search Example 360 List of Figures For More Information On This Product, Go to: www.freescale.com Page MMC2107 – Rev. 2.0 MOTOROLA ...
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... QADC Port QA Data Direction Register (DDRQA 415 QADC Control Register 0 (QACR0 416 QADC Control Register 1 (QACR1 419 QADC Control Register 2 (QACR2 422 QADC Status Register 0 (QASR0 .427 Queue Status Transition 435 QADC Status Register 1 (QASR1 .436 List of Figures Go to: www.freescale.com List of Figures Page Technical Data 33 ...
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... QADC Conversion Queue Operation . . . . . . . . . . . . . . . . . 482 Equivalent Analog Input Circuitry . . . . . . . . . . . . . . . . . . . . 487 Errors Resulting from Clipping . . . . . . . . . . . . . . . . . . . . . . 488 External Positive Edge Trigger Mode Timing With Pause . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 Gated Mode, Single Scan Timing 491 List of Figures For More Information On This Product, Go to: www.freescale.com Page MMC2107 – Rev. 2.0 MOTOROLA ...
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... OnCE Command Register (OCMR 562 OnCE Control Register (OCR 564 OnCE Status Register (OSR .568 OnCE Memory Breakpoint Logic . . . . . . . . . . . . . . . . . . . . 570 OnCE Trace Logic Block Diagram . . . . . . . . . . . . . . . . . . .573 CPU Scan Chain Register (CPUSCR 576 List of Figures Go to: www.freescale.com List of Figures Page Technical Data 35 ...
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... SPI Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603 Test Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 605 Boundary Scan (JTAG) Timing . . . . . . . . . . . . . . . . . . . . . 606 Test Access Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 606 TRST Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606 Debug Event Pin Timing 607 List of Figures For More Information On This Product, Go to: www.freescale.com Page MMC2107 – Rev. 2.0 MOTOROLA ...
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... Reset Controller Module Memory Map 132 Reset Source Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .136 M•CORE Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 Interrupt Controller Module Memory Map 156 MASK Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Priority Select Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . .167 Fast Interrupt Vector Number . . . . . . . . . . . . . . . . . . . . . . . . 170 List of Tables Go to: www.freescale.com List of Tables Page Technical Data 37 ...
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... PEPAR Reset Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 Ports A–I Supported Pin Functions . . . . . . . . . . . . . . . . . . . 258 Edge Port Module Memory Map 263 EPPAx Field Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 Watchdog Timer Module Memory Map . . . . . . . . . . . . . . . . 274 List of Tables For More Information On This Product, Go to: www.freescale.com Page MMC2107 – Rev. 2.0 MOTOROLA ...
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... SPI Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 SS Pin I/O Configurations 377 Bidirectional Pin Configurations . . . . . . . . . . . . . . . . . . . . . . 378 SPI Baud Rate Selection (33-MHz Module Clock 380 SPI Port Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .384 Normal Mode and Bidirectional Mode . . . . . . . . . . . . . . . . . 394 SPI Interrupt Request Sources .397 List of Tables Go to: www.freescale.com List of Tables Page Technical Data 39 ...
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... Chip Select Address Range Encoding . . . . . . . . . . . . . . . . . 531 JTAG Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .542 List of Pins Not Scanned in JTAG Mode . . . . . . . . . . . . . . . 548 Boundary-Scan Register Definition . . . . . . . . . . . . . . . . . . . 549 OnCE Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . 563 List of Tables For More Information On This Product, Go to: www.freescale.com Page ) . . . . . . . . . . . . . . 500 Off MMC2107 – Rev. 2.0 MOTOROLA ...
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... ESD Protection Characteristics . . . . . . . . . . . . . . . . . . . . . . 587 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . 588 PLL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . 590 QADC Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . 591 QADC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . 592 QADC Conversion Specifications 593 FLASH Program and Erase Characteristics . . . . . . . . . . . . . 594 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615 List of Tables Go to: www.freescale.com List of Tables Page Technical Data 41 ...
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... Freescale Semiconductor, Inc. List of Tables Technical Data 42 List of Tables For More Information On This Product, Go to: www.freescale.com MMC2107 – Rev. 2.0 MOTOROLA ...
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... LQFP for applications requiring the full external memory interface support or a large number of general-purpose inputs/outputs (GPIO). ™M•CORE is a trademark of Motorola, Inc. MMC2107 – Rev. 2.0 MOTOROLA For More Information On This Product, Section 1. General Description Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 General Description Go to: www.freescale.com Technical Data 43 ...
Page 44
... Mode fault error flag with CPU interrupt capability – Double-buffered operation – Serial clock with programmable polarity and phase – Control of SPI operation during wait mode – Reduced drive control General Description For More Information On This Product, Go to: www.freescale.com (1) FLASH bit cell MMC2107 – Rev. 2.0 MOTOROLA ...
Page 45
... Programmable input sample time for various source impedances – Two conversion command queues with a total of 64 entries – Subqueues possible using pause mechanism – Queue complete and pause software interrupts available on both queues General Description Go to: www.freescale.com General Description Features Technical Data 45 ...
Page 46
... Ability to generate a separate vector number for normal and fast interrupts – Ability for software to self-schedule interrupts – Software visibility of pending interrupts and interrupt signals to core – Asynchronous operation to support wakeup from low-power modes General Description For More Information On This Product, Go to: www.freescale.com MMC2107 – Rev. 2.0 MOTOROLA ...
Page 47
... Status flag indication of source of last reset Chip configurations: – Support for single-chip, master, emulation, and test modes – System configuration during reset – Bus monitor – Configurable output pad drive strength control General Description Go to: www.freescale.com General Description Features Technical Data 47 ...
Page 48
... Special chip selects support replacement of GPIO with external logic (port replacement logic) – Emulation of internal page mode FLASH support Joint Test Action Group (JTAG) support for system-level board testing General Description For More Information On This Product, Go to: www.freescale.com Figure 1-1. MMC2107 – Rev. 2.0 MOTOROLA ...
Page 49
... For More Information On This Product, SRAM 8-KBYTE M•CORE BUS IPBUS INTERFACE PROGRAMMABLE INTERVAL TIMER 1 PROGRAMMABLE OSC/PLL INTERVAL TIMER 2 WATCHDOG TIMER IPBUS SCI1 SCI2 Figure 1-1. Block Diagram General Description Go to: www.freescale.com General Description Block Diagram FLASH 128-KBYTE DDF SSF D[31:0] A[22:0] R/W ...
Page 50
... Freescale Semiconductor, Inc. General Description Technical Data 50 General Description For More Information On This Product, Go to: www.freescale.com MMC2107 – Rev. 2.0 MOTOROLA ...
Page 51
... For More Information On This Product, Section 2. System Memory Map Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Address Map Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Figure 128 Kbytes of internal FLASH 8 Kbytes of internal static random-access memory (SRAM) Internal memory mapped registers External address space System Memory Map Go to: www.freescale.com 2-1, includes: Technical Data 51 ...
Page 52
... Address Map Technical Data 52 EXTERNAL MEMORY 0x8000_0000 SEE 2.4 Register Map 0x00c0_0000 0x0080_0000 0 Figure 2-1. Address Map System Memory Map For More Information On This Product, Go to: www.freescale.com REGISTERS INTERNAL SRAM 8 KBYTES INTERNAL FLASH 128 KBYTES MMC2107 – Rev. 2.0 MOTOROLA ...
Page 53
... Queued analog-to-digital converter (QADC) 0x00cb_0000 Serial peripheral interface (SPI) 0x00cc_0000 Serial communications interface 1 (SCI1) 0x00cd_0000 Serial communications interface 2 (SCI2) 0x00ce_0000 0x00cf_0000 0x00d0_0000 System Memory Map Go to: www.freescale.com System Memory Map Address Map (1) Usage (2) Ports (PORTS) Chip configuration (CCM) Chip selects (CS) Clocks (CLOCK) ...
Page 54
... Write: Reset Bit Read: PORTG7 PORTG6 PORTG5 PORTG4 Write: Reset Writes have no effect and the access terminates without a transfer error exception. System Memory Map For More Information On This Product, Go to: www.freescale.com Bit Number PORTA3 PORTA2 PORTA1 PORTA0 PORTB3 PORTB2 PORTB1 PORTB0 ...
Page 55
... DDRD7 DDRD6 DDRD5 DDRD4 Write Bit Read: DDRE7 DDRE6 DDRE5 DDRE4 Write Writes have no effect and the access terminates without a transfer error exception. System Memory Map Go to: www.freescale.com System Memory Map Register Map Bit Number PORTH3 PORTH2 PORTH1 PORTH0 PORTI3 PORTI2 ...
Page 56
... Read: PORTCP7 PORTCP6 PORTCP5 PORTCP4 PORTCP3 PORTCP2 PORTCP1 PORTCP0 Write: SETC7 SETC6 SETC5 Reset Writes have no effect and the access terminates without a transfer error exception. System Memory Map For More Information On This Product, Go to: www.freescale.com Bit Number DDRF4 DDRF3 DDRF2 DDRF1 0 0 ...
Page 57
... Writes have no effect, reads return 0s, and the access terminates without a transfer error exception. Bit Read Write: CLRA7 CLRA6 CLRA5 CLRA4 Writes have no effect and the access terminates without a transfer error exception. System Memory Map Go to: www.freescale.com System Memory Map Register Map Bit Number SETD3 SETD2 SETD1 ...
Page 58
... Write: CLRG7 CLRG6 CLRG5 Reset Bit Read Write: CLRH7 CLRH6 CLRH5 Reset Writes have no effect and the access terminates without a transfer error exception. System Memory Map For More Information On This Product, Go to: www.freescale.com Bit Number CLRB4 CLRB3 CLRB2 CLRB1 CLRC4 CLRC3 ...
Page 59
... Writes have no effect, reads return 0s, and the access terminates without a transfer error exception. Bit Ports register space (block of 0x00c0_0000 through 0x00c0_oo3f) is mirrored/repeated. = Writes have no effect and the access terminates without a transfer error exception. System Memory Map Go to: www.freescale.com System Memory Map Register Map Bit Number ...
Page 60
... Bit Read RPLLSEL RPLLREF RLOAD Write: Reset Writes have no effect and the access terminates without a transfer error exception. System Memory Map For More Information On This Product, Go to: www.freescale.com Bit Number MODE2 MODE1 EMINT Note 2 0 Note 1 Note SHINT BME BMD ...
Page 61
... Access results in the module generating an access termination transfer error. Bit Access results in a bus monitor timeout generating an access termination transfer error. = Writes have no effect and the access terminates without a transfer error exception. System Memory Map Go to: www.freescale.com System Memory Map Register Map Bit Number ...
Page 62
... Note: Reset state determined during reset configuration Bit Read Write: Reset Bit Read Write: Reset Writes have no effect and the access terminates without a transfer error exception. System Memory Map For More Information On This Product, Go to: www.freescale.com Bit Number WWS WE WS2 WS1 TAEN ...
Page 63
... Note 1 Note 1 Note 2 Notes: 1. Reset state determined during reset configuration 2. See the LOCKS and LOCK bit descriptions. = Writes have no effect and the access terminates without a transfer error exception. System Memory Map Go to: www.freescale.com System Memory Map Register Map Bit Number WWS ...
Page 64
... Access results in a bus monitor timeout generating an access termination transfer error. Bit Read: 0 FRC- SOFTRST RSTOUT Write: Reset Writes have no effect and the access terminates without a transfer error exception. System Memory Map For More Information On This Product, Go to: www.freescale.com Bit Number ...
Page 65
... Read MASK4 Write Bit Read Write Bit Read: 0 VEC6 VEC5 Write Writes have no effect and the access terminates without a transfer error exception. System Memory Map Go to: www.freescale.com System Memory Map Register Map Bit Number WDR POR EXT LOC Reset dependent ...
Page 66
... IF22 IF21 Write: Reset Bit Read: IF15 IF14 IF13 Write: Reset Bit Read: IF7 IF6 IF5 Write: Reset Writes have no effect and the access terminates without a transfer error exception. System Memory Map For More Information On This Product, Go to: www.freescale.com Bit Number ...
Page 67
... Read: NIE15 NIE14 NIE13 Write Bit Read: NIE7 NIE6 NIE5 Write Writes have no effect and the access terminates without a transfer error exception. System Memory Map Go to: www.freescale.com System Memory Map Register Map Bit Number IP28 IP27 IP26 IP25 IP20 IP19 IP18 ...
Page 68
... FIE13 Write: Reset Bit Read: FIE7 FIE6 FIE5 Write: Reset Writes have no effect and the access terminates without a transfer error exception. System Memory Map For More Information On This Product, Go to: www.freescale.com Bit Number NIP28 NIP27 NIP26 NIP25 NIP20 NIP19 NIP18 NIP17 ...
Page 69
... Access results in the module generating an access termination transfer error. Bit Access results in a bus monitor timeout generating an access termination transfer error. = Writes have no effect and the access terminates without a transfer error exception. System Memory Map Go to: www.freescale.com System Memory Map Register Map Bit Number ...
Page 70
... Write: Reset Bit Writes have no effect, reads return 0s, and the access terminates without a transfer error exception. = Writes have no effect and the access terminates without a transfer error exception. System Memory Map For More Information On This Product, Go to: www.freescale.com Bit Number EPPA5 EPPA4 ...
Page 71
... WM6 WM5 Write Bit Read: WC15 WC14 WC13 Write Bit Read: WC7 WC6 WC5 Write Writes have no effect and the access terminates without a transfer error exception. System Memory Map Go to: www.freescale.com System Memory Map Register Map Bit Number WAIT DOZE DBG 0 1 ...
Page 72
... PM13 Write: Reset Bit Read: PM7 PM6 PM5 Write: Reset Writes have no effect and the access terminates without a transfer error exception. System Memory Map For More Information On This Product, Go to: www.freescale.com Bit Number WS12 WS11 WS10 WS9 WS4 WS3 WS2 WS1 ...
Page 73
... Access results in the module generating an access termination transfer error if not in test mode. Bit Access results in the module generating an access termination transfer error if not in test mode. = Writes have no effect and the access terminates without a transfer error exception. System Memory Map Go to: www.freescale.com System Memory Map Register Map Bit Number ...
Page 74
... Read MUX Write: Reset Bit Read: PSH7 PSH6 PSH5 Write: Reset Writes have no effect and the access terminates without a transfer error exception. System Memory Map For More Information On This Product, Go to: www.freescale.com Bit Number PQA4 PQA3 PQA1 PQB3 PQB2 PQB1 ...
Page 75
... BQ25 Write Bit Read: CF1 PF1 CF2 Write Bit Read: QS7 QS6 CWP5 CWP4 Write Writes have no effect and the access terminates without a transfer error exception. System Memory Map Go to: www.freescale.com System Memory Map Register Map Bit Number MQ111 MQ110 MQ19 ...
Page 76
... Write: Reset Bit Read Write: Reset Bit Read: Write: Reset: = Writes have no effect and the access terminates without a transfer error exception. System Memory Map For More Information On This Product, Go to: www.freescale.com Bit Number CWPQ13 CWPQ12 CWPQ11 CWPQ10 CWPQ23 CWPQ22 CWPQ21 CWPQ20 ...
Page 77
... Access results in a bus monitor timeout generating an access termination transfer error. Bit Read: SPIE SPE SWOM MSTR Write Bit Read Write Writes have no effect and the access terminates without a transfer error exception. System Memory Map Go to: www.freescale.com System Memory Map Register Map Bit Number RESULT RESULT ...
Page 78
... Bit Writes have no effect, reads return 0s, and the access terminates without a transfer error exception. = Writes have no effect and the access terminates without a transfer error exception. System Memory Map For More Information On This Product, Go to: www.freescale.com Bit Number SPPR4 SPR2 SPR1 ...
Page 79
... TCIE RIE Write Bit Read: TDRE TC RDRF Write Bit Read Write Writes have no effect and the access terminates without a transfer error exception. System Memory Map Go to: www.freescale.com System Memory Map Register Map Bit Number SBR11 SBR10 SBR9 SBR4 SBR3 SBR2 SBR1 ...
Page 80
... Writes have no effect, reads return 0s, and the access terminates without a transfer error exception. Bit Access results in a bus monitor timeout generating an access termination transfer error. = Writes have no effect and the access terminates without a transfer error exception. System Memory Map For More Information On This Product, Go to: www.freescale.com Bit Number ...
Page 81
... Read: Bit Write Bit Read: Bit Write Bit Read TIMEN TFFCA Write Writes have no effect and the access terminates without a transfer error exception. System Memory Map Go to: www.freescale.com System Memory Map Register Map Bit Number IOS3 IOS2 IOS1 FOC3 FOC2 FOC1 ...
Page 82
... Bit Read: 0 TOI PUPT Write: Reset Bit Read Write: Reset Writes have no effect and the access terminates without a transfer error exception. System Memory Map For More Information On This Product, Go to: www.freescale.com Bit Number TOV3 TOV2 TOV1 OL2 OM1 OL1 OM0 ...
Page 83
... Write Bit Read: Bit Write Bit Read: Bit Write Bit Read: Bit Write Bit Read: Bit Write Writes have no effect and the access terminates without a transfer error exception. System Memory Map Go to: www.freescale.com System Memory Map Register Map Bit Number ...
Page 84
... Writes have no effect, reads return 0s, and the access terminates without a transfer error exception. Bit Read Write: Reset Bit Read Write: Reset Writes have no effect and the access terminates without a transfer error exception. System Memory Map For More Information On This Product, Go to: www.freescale.com Bit Number PEDGE CLK1 CLK0 PAOVI ...
Page 85
... DATA4 Write Bit Read: PROTECT7 PROTECT6 PROTECT5 PROTECT4 PROTECT3 PROTECT2 PROTECT1 PROTECT0 Write Reset state is defined by reset override. = Writes have no effect and the access terminates without a transfer error exception. System Memory Map Go to: www.freescale.com System Memory Map Register Map Bit Number ...
Page 86
... Write: Reset Bit Read: BLOCK7 BLOCK6 BLOCK5 BLOCK4 Write: Reset Bit Read RSVD6 Write: Reset Writes have no effect and the access terminates without a transfer error exception. System Memory Map For More Information On This Product, Go to: www.freescale.com Bit Number NVR PAWS2 PAWS1 ...
Page 87
... Access results in the module generating an access termination transfer error. Bit Access results in a bus monitor timeout generating an access termination transfer error. = Writes have no effect and the access terminates without a transfer error exception. System Memory Map Go to: www.freescale.com System Memory Map Register Map Bit 0 3 ...
Page 88
... Freescale Semiconductor, Inc. System Memory Map Technical Data 88 System Memory Map For More Information On This Product, Go to: www.freescale.com MMC2107 – Rev. 2.0 MOTOROLA ...
Page 89
... Chip Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Reset Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Chip Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Boot Device Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Output Pad Strength Configuration . . . . . . . . . . . . . . . . . .105 Clock Mode Selection 105 Internal FLASH Configuration . . . . . . . . . . . . . . . . . . . . . . 106 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Interrupts 106 Chip Configuration Module (CCM) Go to: www.freescale.com Technical Data 89 ...
Page 90
... Selects output pad strength Selects boot device Selects module configuration Selects bus monitor configuration Master mode Single-chip mode Emulation mode FAST mode for factory test only Chip Configuration Module (CCM) For More Information On This Product, Go to: www.freescale.com MMC2107 – Rev. 2.0 MOTOROLA ...
Page 91
... Factory Access Slave Test (FAST) Mode FAST mode is for factory test only. MMC2107 – Rev. 2.0 MOTOROLA For More Information On This Product, Chip Configuration Module (CCM) Go to: www.freescale.com Chip Configuration Module (CCM) Modes of Operation Technical Data 91 ...
Page 92
... CCM signals. For more detailed Section 4. Signal Table 3-1. Signal Properties Function Reset configuration select Clock mode select Reset configuration overrides Chip Configuration Module (CCM) For More Information On This Product, Go to: www.freescale.com OUTPUT PAD STRENGTH SELECTION CLOCK MODE SELECTION MODULE CONFIGURATION Description. Reset State Internal weak pullup device — ...
Page 93
... The chip test register (CTR) contains chip-specific test functions. shows the accessibility of write-once bits. Table 3-2. Write-Once Bits Read/Write Accessibility Configuration Chip Configuration Module (CCM) Go to: www.freescale.com Chip Configuration Module (CCM) Memory Map and Registers Read/Write Access Read-always Write-always Write-always ...
Page 94
... SZEN PSTEN SHINT 0 Note 3 Note Writes have no effect and the access terminates without a transfer error exception. Figure 3-2. Chip Configuration Register (CCR) Chip Configuration Module (CCM) For More Information On This Product, Go to: www.freescale.com Bits 15–0 Access (2) S Reserved S (2) S Reserved — ...
Page 95
... CS1 decodes external memory address space. 3-4. Table 3-4. Chip Configuration Mode Selection MODE[2:0] 111 Master mode 110 Single-chip mode 10X FAST mode 0XX Emulation mode Chip Configuration Module (CCM) Go to: www.freescale.com Chip Configuration Module (CCM) Memory Map and Registers Chip Configuration Mode Technical Data 95 ...
Page 96
... Bus monitor enabled on external bus cycles 0 = Bus monitor disabled on external bus cycles shows the read/write accessibility of this write-once bit Bus monitor enabled in debug mode 0 = Bus monitor disabled in debug mode Chip Configuration Module (CCM) For More Information On This Product, Go to: www.freescale.com MMC2107 – Rev. 2.0 MOTOROLA ...
Page 97
... Bit Bit RPLLREF RLOAD Writes have no effect and the access terminates without a transfer error exception. Figure 3-3. Reset Configuration Register (RCON) Chip Configuration Module (CCM) Go to: www.freescale.com Chip Configuration Module (CCM) Memory Map and Registers Timeout Period (in System Clocks Bit Bit ...
Page 98
... Full drive strength 0 = Default drive strength 1 = Boot device uses 32-bit port Boot device uses 16-bit port Boot from external boot device 0 = Boot from internal boot device Chip Configuration Module (CCM) For More Information On This Product, Go to: www.freescale.com MMC2107 – Rev. 2.0 MOTOROLA ...
Page 99
... Bit PRN7 PRN6 PRN5 PRN4 Writes have no effect and the access terminates without a transfer error exception. Figure 3-4. Chip Identification Register (CIR) Chip Configuration Module (CCM) Go to: www.freescale.com Chip Configuration Module (CCM) Memory Map and Registers Bit PIN3 PIN2 PIN1 PIN0 ...
Page 100
... These functions are described here. Technical Data 100 Bit Bit Writes have no effect and the access terminates without a transfer error exception. Figure 3-5. Chip Test Register (CTR) Chip Configuration Module (CCM) For More Information On This Product, Go to: www.freescale.com Bit Bit MMC2107 – Rev. 2.0 MOTOROLA ...
Page 101
... Function Digital I/O or primary function RCON function for all (2) modes Not affected Table 3-7.) The internal configuration signals are driven to reflect Chip Configuration Module (CCM) Go to: www.freescale.com Chip Configuration Module (CCM) Functional Description Output Input I/O (1) State State Must be driven Input — ...
Page 102
... Normal PLL mode w/crystal oscillator reference D28 V 1 Internal FLASH enabled DD 0 Internal FLASH disabled Chip Configuration Module (CCM) For More Information On This Product, Go to: www.freescale.com (1) Function Chip Mode Selected Boot Device Output Pad Drive Strength Clock Mode Module Configuration MMC2107 – Rev. 2.0 MOTOROLA ...
Page 103
... Mode MODE2 D26 driven high D26 driven high D26 driven high D26 driven low Table 3-9. Chip Configuration Module (CCM) Go to: www.freescale.com Chip Configuration Module (CCM) Functional Description Table 3-8 shows the mode (1) MODE1 MODE0 D17 driven high D16 driven high ...
Page 104
... Chip Select CS0 Control 3-10. Table 3-10. Boot Device Selection CSEN Bit D18 driven low D18 driven high D18 driven high Chip Configuration Module (CCM) For More Information On This Product, Go to: www.freescale.com CSCR0 CSCR1 Register Register CSEN Bit PS Bit CSEN Bit 0 ...
Page 105
... DDSYN V driven high DDSYN V driven high DDSYN V driven high DDSYN Chip Configuration Module (CCM) Go to: www.freescale.com Chip Configuration Module (CCM) Functional Description (1) CCR Register LOAD Bit D21 driven low D2 driven high (1) PLLSEL Bit PLLREF Bit D23 don’t care D22 don’t care D23 driven low D22 don’ ...
Page 106
... Table 3-13. Internal FLASH Configuration Internal FLASH Configuration Registers. The CCM controls chip configuration 3.8 Functional Chip Configuration Module (CCM) For More Information On This Product, Go to: www.freescale.com Table 3-13. (1) External D28 State D28 pin driven high D28 pin driven low Description. MMC2107 – ...
Page 107
... Transfer Error Acknowledge (TEA 123 Emulation Mode Chip Selects (CSE[1:0 123 Transfer Code (TC[2:0 123 Read/Write (R/W 123 Address Bus (A[22:0 124 Enable Byte (EB[3:0 124 Chip Select (CS[3:0 124 Output Enable (OE .124 Signal Description Go to: www.freescale.com and 122 SSSYN Technical Data 107 ...
Page 108
... DDF SSF Standby Power (V STBY Positive Supply ( 128 DD Ground ( .128 SS Signal Description For More Information On This Product, Go to: www.freescale.com and 126 RL and .126 SSA ) . . . . . . . . . . . . . . . . . . . . . . . . . 126 ) . . . . . . . . . . . . 128 128 MMC2107 – Rev. 2.0 MOTOROLA ...
Page 109
... Provide enhanced support for development purposes 23 address output lines Four chip selects Two emulation chip selects Four byte/write enables Read/write (R/W) signal Output enable signal Three transfer code signals Six power/ground pins Signal Description Go to: www.freescale.com Signal Description Introduction Technical Data 109 ...
Page 110
... Signal Description For More Information On This Product, Go to: www.freescale.com Pin Name D30 / PA6 D29 / PA5 D28 / PA4 D27 / PA3 D26 / PA2 A11 D25 / PA1 D24 / PA0 A10 D23 / PB7 A9 A8 D22 / PB6 D21 / PB5 D20 / PB4 D19 / PB3 ...
Page 111
... Signal Description Go to: www.freescale.com Signal Description Package Pinout Summary Pin Name D16 / PB0 A5 D15 / PC7 A4 A3 D14 / PC6 D13 / PC5 D12 / PC4 D11 / PC3 D10 / PC2 D9 / PC1 D8 / PC0 D7 / PD7 D6 / PD6 D5 / PD5 D4 / PD4 D3 / PD3 PD2 PD1 A1 A0 ...
Page 112
... Signal Description For More Information On This Product, Go to: www.freescale.com Pin Name ICOC13 ICOC12 ICOC11 R/W CSE1 ICOC10 CSE0 TEST TXD2 TC2 RXD2 TXD1 RXD1 INT0 INT1 V SSF V DDF INT2 TC1 INT3 TC0 CS3 INT4 CS2 INT5 CS1 MMC2107 – ...
Page 113
... Signal Description Go to: www.freescale.com Signal Description Package Pinout Summary Pin Name CS0 V PP INT6 INT7 MOSI MISO V STBY SCK SS OE EB3 SHS / PE7 EB2 TA / PE6 EB1 EB0 TEA / PE5 V DDH ...
Page 114
... Signal Description For More Information On This Product, Go to: www.freescale.com Pin Name A22 A21 RESET A20 RSTOUT A19 A18 V DDSYN XTAL EXTAL V SSSYN V SS CLKOUT V DD TCLK A17 ...
Page 115
... D12 35 D11 36 D10 Figure 4-1. 144-Pin LQFP Assignments MMC2107 – Rev. 2.0 MOTOROLA For More Information On This Product, Signal Description Go to: www.freescale.com Signal Description Package Pinout Summary PQA4 108 PQB0 107 PQB1 106 PQB2 105 PQB3 104 V 103 DDH TEA 102 ...
Page 116
... PB3 14 PB2 15 PB1 16 PB0 17 PC7 18 PC6 19 PC5 PC4 23 PC3 24 PC2 25 Figure 4-2. 100-Pin LQFP Assignments Technical Data 116 Signal Description For More Information On This Product, Go to: www.freescale.com PQA4 75 PQB0 74 PQB1 73 PQB2 72 PQB3 DDH PE5 69 PE6 68 PE7 SCK STBY MISO 63 MOSI 62 INT7 ...
Page 117
... (6) 1 — — I/O Edge Port Signal Description Go to: www.freescale.com Signal Description Package Pinout Summary Drive Output Strength (4) Driver Pullup (3) Control (ST/OD/SP) — Pullup — LOAD — ST — — SP — — SP LOAD — ST — — — — ...
Page 118
... Queued Analog-to-Digital Converter (QADC — — — — — — — — — — Signal Description For More Information On This Product, Go to: www.freescale.com Drive Output Strength (4) Driver Pullup (2) (3) Control (ST/OD/SP) (4) RDPSP0 Pullup (4) RDPSP0 Pullup (4) RDPSP0 Pullup (4) RDPSP0 Pullup (4) RDPSCI0 Pullup ...
Page 119
... I — — — — — — — — — — 100 144 Signal Description Go to: www.freescale.com Signal Description Package Pinout Summary Drive Output Strength (4) Driver Pullup (3) Control (ST/OD/SP) — Pullup — — Pullup — — Pullup — — Pullup — ...
Page 120
... If the internal reset is not asserted and the FRCRSTOUT bit is not set and the SHOWINT bit is not set, then the RSTOUT signal will be negated to indicate to the system that there is no reset condition. Signal Description For More Information On This Product, Go to: www.freescale.com MMC2107 – Rev. 2.0 MOTOROLA ...
Page 121
... INT[7:6] will be used to reflect the state of the TSIZ[1:0] signals from the M•CORE. If the PSTEN bit in the chip configuration register is set, then INT[5:2] will be used to reflect the state of the PSTAT[3:0] signals from the M•CORE. Signal Description Go to: www.freescale.com Signal Description Signal Descriptions Technical Data 121 ...
Page 122
... Data Bus (D[31:0]) These three-state bidirectional signals provide the general-purpose data path between the microcontroller unit (MCU) and all other devices. Technical Data 122 and V ) DDSYN SSSYN Signal Description For More Information On This Product, Go to: www.freescale.com MMC2107 – Rev. 2.0 MOTOROLA ...
Page 123
... This output signal indicates the direction of the data transfer on the bus. A logic 1 indicates a read from a slave device and a logic 0 indicates a write to a slave device. MMC2107 – Rev. 2.0 MOTOROLA For More Information On This Product, Signal Description Go to: www.freescale.com Signal Description Signal Descriptions Technical Data 123 ...
Page 124
... These bidirectional signals function as either external interrupt sources or GPIO. Also, these signals may be used to reflect the internal PSTAT[3:0] signals and externally to provide an indication of the M•CORE processor status. Technical Data 124 Signal Description For More Information On This Product, Go to: www.freescale.com MMC2107 – Rev. 2.0 MOTOROLA ...
Page 125
... These signals are used for the SCI receiver data input and are also available for GPIO when not configured for receiver operation. MMC2107 – Rev. 2.0 MOTOROLA For More Information On This Product, Signal Description Go to: www.freescale.com Signal Description Signal Descriptions Technical Data 125 ...
Page 126
... Positive Supply (V DDH This signal supplies positive power to the ESD structures in the QADC pads. Technical Data 126 and and V ) SSA ) Signal Description For More Information On This Product, Go to: www.freescale.com ) and low (V ) reference potentials RL MMC2107 – Rev. 2.0 MOTOROLA ...
Page 127
... CPU has entered debug mode as a result of a debug request or a breakpoint condition input, this signal provides multiple functions. MMC2107 – Rev. 2.0 MOTOROLA For More Information On This Product, Signal Description Go to: www.freescale.com Signal Description Signal Descriptions Technical Data 127 ...
Page 128
... This signal supplies positive power to the core logic and I/O pads. 4.5.11.5 Ground ( This signal is the negative supply (ground) to the chip. Technical Data 128 to prevent unintentional activation of test functions and V DDF ) ) DD Signal Description For More Information On This Product, Go to: www.freescale.com ) SSF MMC2107 – Rev. 2.0 MOTOROLA is DD ...
Page 129
... Loss of Lock Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Reset Control Flow 138 Synchronous Reset Requests . . . . . . . . . . . . . . . . . . . . 138 Internal Reset Request . . . . . . . . . . . . . . . . . . . . . . . . . 140 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Concurrent Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Reset Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Reset Status Flags 141 Interrupts 141 Reset Controller Module Go to: www.freescale.com Technical Data 129 ...
Page 130
... PLL loss of clock – Software Software can assert external RSTOUT pin independent of chip reset state. Software readable status flags indicating the cause of the last reset Reset Controller Module For More Information On This Product, Go to: www.freescale.com MMC2107 – Rev. 2.0 MOTOROLA ...
Page 131
... Section 4. Signal Table 5-1. Reset Controller Signal Properties Input Alternate Direction Hysteresis — SHOWINT O — Reset Controller Module Go to: www.freescale.com Reset Controller Module Block Diagram RSTOUT PIN TO INTERNAL RESETS Description. Input (1) Pullup Synchronization ( — ...
Page 132
... Reset test register (RTR) — Used only for factory test Table 5-2. Reset Controller Module Memory Map Address Reset control register (RCR) Reset status register (RSR) Reset test register (RTR) Reset Controller Module For More Information On This Product, Go to: www.freescale.com Bits 7–0 Access S/U S/U S/U (2) Reserved MMC2107 – ...
Page 133
... Writes have no effect and the access terminates without a transfer error exception. Figure 5-2. Reset Control Register (RCR Request software reset software reset request 1 = Assert the RSTOUT pin not assert the RSTOUT pin. Reset Controller Module Go to: www.freescale.com Reset Controller Module Memory Map and Registers Bit 0 ...
Page 134
... Last reset caused by software software reset 1 = Last reset caused by watchdog timer timeout watchdog timer timeout reset 1 = Last reset caused by power-on reset 0 = Last reset not caused by power-on reset Reset Controller Module For More Information On This Product, Go to: www.freescale.com Bit 0 POR EXT LOC ...
Page 135
... Last reset caused by loss of lock loss of lock Bit Writes have no effect and the access terminates without a transfer error exception. Figure 5-4. Reset Test Register (RTR) Reset Controller Module Go to: www.freescale.com Reset Controller Module Memory Map and Registers Bit Technical Data 135 ...
Page 136
... Reset is asserted immediately to the system. Technical Data 136 defines the sources of reset and the signals driven by the reset Table 5-3. Reset Source Summary Source Reset Controller Module For More Information On This Product, Go to: www.freescale.com Type Asynchronous Synchronous Asynchronous Synchronous Asynchronous Asynchronous Synchronous MMC2107 – ...
Page 137
... RSTOUT for approximately 512 cycles after the PLL has acquired lock. The part then exits reset and begins operation. MMC2107 – Rev. 2.0 MOTOROLA For More Information On This Product, has reached a minimum acceptable level and, DD Reset Controller Module Go to: www.freescale.com Reset Controller Module Functional Description Technical Data 137 ...
Page 138
... PLL lock (9A), the reset flow switches to (8) and waits for the RESET pin to be negated before continuing. Technical Data 138 shows the reset logic control flow. In the flow description that Reset Controller Module For More Information On This Product, Go to: www.freescale.com MMC2107 – Rev. 2.0 MOTOROLA ...
Page 139
... ASSERT RSTOUT AND LATCH RESET STATUS 8 RESET NEGATED PLL MODE WAIT 512 CLKOUT CYCLES 11 RCON ASSERTED? N Figure 5-5. Reset Control Flow Reset Controller Module Go to: www.freescale.com Reset Controller Module Functional Description 0 POR 4 ASSERT RSTOUT AND LATCH RESET STATUS PLL LOCKED? Y 11A ...
Page 140
... RESET pin to negate (8 loss of clock or loss of lock condition is detected during the 512-cycle wait, the reset sequence continues after a PLL lock (9, 9A). Technical Data 140 Reset Controller Module For More Information On This Product, Go to: www.freescale.com MMC2107 – Rev. 2.0 MOTOROLA ...
Page 141
... EXT bit along with the LOC and/or LOL bits are set. 5.8 Interrupts The reset controller does not generate interrupt requests. MMC2107 – Rev. 2.0 MOTOROLA For More Information On This Product, Reset Controller Module Go to: www.freescale.com Reset Controller Module Interrupts Technical Data 141 ...
Page 142
... Freescale Semiconductor, Inc. Reset Controller Module Technical Data 142 Reset Controller Module For More Information On This Product, Go to: www.freescale.com MMC2107 – Rev. 2.0 MOTOROLA ...
Page 143
... MMC2107 – Rev. 2.0 MOTOROLA M•CORE M210 Central Processor Unit (CPU) For More Information On This Product, Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Microarchitecture Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Data Format Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Operand Addressing Capabilities . . . . . . . . . . . . . . . . . . . . . . 150 Instruction Set Overview 150 Go to: www.freescale.com Technical Data 143 ...
Page 144
... Fast interrupt support, with 16 entry user-controlled alternate register file Vectored and autovectored interrupt support On-chip emulation support Full static design for minimal power consumption M•CORE M210 Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com MMC2107 – Rev. 2.0 MOTOROLA ...
Page 145
... M•CORE M210 Central Processor Unit (CPU block diagram of the M•CORE processor. CONTROL REGISTER FILE 32 BITS PORT IMMEDIATE MUX SCALE MUX H/W ACCELERATOR INTERFACE BUS DATA BUS Go to: www.freescale.com Microarchitecture Summary ADDRESS GENERATION ADDRESS MUX ADDRESS BUS PC BRANCH INCREMENT ADDER INSTRUCTION PIPELINE INSTRUCTION DECODE Technical Data ...
Page 146
... Fast interrupts take precedence over normal interrupts. Both types have dedicated exception shadow registers. For service requests of either kind, an automatic vector is generated when the request is made. Technical Data 146 M•CORE M210 Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com MMC2107 – Rev. 2.0 MOTOROLA ...
Page 147
... R10 R11 R11 R12 R12 R13 R13 R14 R14 R15 R15 SUPERVISOR PROGRAMMER’S MODEL MODEL Figure 6-2. Programming Model Go to: www.freescale.com Programming Model ALTERNATE FILE CR0 PSR VBR CR1 EPSR CR2 CR3 FPSR CR4 EPC FPC CR5 SS0 CR6 CR7 ...
Page 148
... A single register is provided to alter the base address of the exception vector table. Two registers are provided for global control and status. Technical Data 148 M•CORE M210 Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com MMC2107 – Rev. 2.0 MOTOROLA ...
Page 149
... BYTE 6 BYTE 7 BYTE 9 BYTE A BYTE B BYTE D BYTE E BYTE HALF-WORD 16 15 HALF-WORD BYTE 1 BYTE 2 Go to: www.freescale.com Data Format Summary 0 WORD AT 0X0000 000 0 WORD AT 0X0000 000 4 WORD AT 0X0000 000 8 WORD AT 0X0000 000 C 0 BYTE SIGNED BYTE 0 BYTE UNSIGNED BYTE 0 SIGNED HALF-WORD 0 UNSIGNED HALF-WORD ...
Page 150
... Add with C Bit Add Immediate Add Unsigned Logical AND Logical AND Immediate AND NOT Arithmetic Shift Right Arithmetic Shift Right, Update C Bit M•CORE M210 Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com Description MMC2107 – Rev. 2.0 MOTOROLA ...
Page 151
... Load Multiple Registers Load Register Quadrant Decrement with C-Bit Update and Branch if Condition True Load Relative Word Logical Shift Left and Right Logical Shift Left and Right, Update C Bit Logical Shift Left and Right by Immediate Go to: www.freescale.com Instruction Set Overview Technical Data 151 ...
Page 152
... Test for No Byte Equal Zero Wait Exclusive OR Extended Shift Right Extract Byte 0 Extract Byte 1 Extract Byte 2 Extract Byte 3 Zero-Extend Byte Zero-Extend Half-Word M•CORE M210 Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com Description MMC2107 – Rev. 2.0 MOTOROLA ...
Page 153
... Interrupt Sources and Prioritization . . . . . . . . . . . . . . . . . .168 Fast and Normal Interrupt Requests . . . . . . . . . . . . . . . . . 168 Autovectored and Vectored Interrupt Requests . . . . . . . . .169 Interrupt Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 M•CORE Processor Configuration . . . . . . . . . . . . . . . . . 171 Interrupt Controller Configuration 171 Interrupt Source Configuration . . . . . . . . . . . . . . . . . . . . 172 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Interrupt Controller Module Go to: www.freescale.com Technical Data 153 ...
Page 154
... Ability to generate a separate vector number for normal and fast interrupts Ability for software to self-schedule interrupts Software visibility of pending interrupts and interrupt signals to core Asynchronous operation to support wakeup from low-power modes Interrupt Controller Module For More Information On This Product, Go to: www.freescale.com MMC2107 – Rev. 2.0 MOTOROLA ...
Page 155
... FMASK & NMASK R OR & MASK DECODE & FMASK & MFI Interrupt Controller Module Go to: www.freescale.com Interrupt Controller Module Block Diagram 32-TO-5 U PRIORITY ENCODER Y VECTOR & N NUMBER FVE C & & NORMAL AND FAST S INTERRUPTS Y N ICR C ISR AUTOVECTOR AE SELECT NMASK Table ...
Page 156
... PLSR10 PLSR13 PLSR14 PLSR17 PLSR18 PLSR21 PLSR22 PLSR25 PLSR26 PLSR29 PLSR30 PLSR33 PLSR34 PLSR37 PLSR38 (2) Unimplemented Interrupt Controller Module For More Information On This Product, Go to: www.freescale.com (1) Bits 7–0 Access S/U S/U S/U S/U S/U S/U S/U S/U — PLSR3 S PLSR7 S PLSR11 S ...
Page 157
... Figure 7-2. Interrupt Control Register (ICR Autovectored interrupt requests 0 = Vectored interrupt requests 1 = Unique vector numbers for fast vectored interrupt requests 0 = Same vector number for fast and normal vectored interrupt requests Interrupt Controller Module Go to: www.freescale.com Interrupt Controller Module Memory Map and Registers Bit 8 ...
Page 158
... Table 7-2. MASK Encoding MASK[4:0] Decimal Binary 0 00000 1 00001 2 00010 3 00011 • • • 31 11111 Interrupt Controller Module For More Information On This Product, Go to: www.freescale.com Masked Priority Levels 0 1–0 2–0 3–0 • • • • • • 31–0 MMC2107 – Rev. 2.0 MOTOROLA ...
Page 159
... Writes have no effect and the access terminates without a transfer error exception. Figure 7-3. Interrupt Status Register (ISR Normal interrupt request asserted 0 = Normal interrupt request negated 1 = Fast interrupt request asserted 0 = Fast interrupt request negated Interrupt Controller Module Go to: www.freescale.com Interrupt Controller Module Memory Map and Registers Bit 8 ...
Page 160
... Bit Bit Bit IF39 IF38 IF37 IF36 Writes have no effect and the access terminates without a transfer error exception. Figure 7-4. Interrupt Force Register High (IFRH) Interrupt Controller Module For More Information On This Product, Go to: www.freescale.com Bit Bit Bit Bit 0 IF35 ...
Page 161
... IF12 Bit IF7 IF6 IF5 IF4 Figure 7-5. Interrupt Force Register Low (IFRL Force interrupt request 0 = Interrupt source not forced Interrupt Controller Module Go to: www.freescale.com Interrupt Controller Module Memory Map and Registers Bit 24 IF27 IF26 IF25 IF24 Bit 16 IF19 IF18 IF17 ...
Page 162
... Writes have no effect and the access terminates without a transfer error exception. Figure 7-6. Interrupt Pending Register (IPR least one interrupt request asserted at priority level All interrupt requests at level x negated Interrupt Controller Module For More Information On This Product, Go to: www.freescale.com Bit 24 IP27 ...
Page 163
... NIE12 Bit NIE7 NIE6 NIE5 NIE4 Figure 7-7. Normal Interrupt Enable Register (NIER Normal interrupt request enabled 0 = Normal interrupt request disabled Interrupt Controller Module Go to: www.freescale.com Interrupt Controller Module Memory Map and Registers Bit 24 NIE27 NIE26 NIE25 NIE24 Bit 16 NIE19 NIE18 ...
Page 164
... Writes have no effect and the access terminates without a transfer error exception. Figure 7-8. Normal Interrupt Pending Register (NIPR least one normal interrupt request asserted at priority level All normal interrupt requests at priority level x negated Interrupt Controller Module For More Information On This Product, Go to: www.freescale.com Bit 24 NIP27 ...
Page 165
... FIE13 FIE12 Bit FIE7 FIE6 FIE5 FIE4 Figure 7-9. Fast Interrupt Enable Register (FIER Fast interrupt enabled 0 = Fast interrupt disabled Interrupt Controller Module Go to: www.freescale.com Interrupt Controller Module Memory Map and Registers Bit 24 FIE27 FIE26 FIE25 FIE24 Bit 16 FIE19 FIE18 FIE17 ...
Page 166
... Writes have no effect and the access terminates without a transfer error exception. Figure 7-10. Fast Interrupt Pending Register (FIPR least one fast interrupt request asserted at priority level Any fast interrupt requests at priority level x negated Interrupt Controller Module For More Information On This Product, Go to: www.freescale.com Bit 24 FIP27 ...
Page 167
... Table 7-3. Priority Select Encoding PLS[4:0] Priority Level 00000 0 (lowest) 00001–11110 1–30 11111 31 (highest) Interrupt source prioritization Fast and normal interrupt requests Autovectored and vectored interrupt requests Interrupt configuration Interrupt Controller Module Go to: www.freescale.com Interrupt Controller Module Functional Description Bit 0 PLS3 PLS2 PLS1 PLS0 ...
Page 168
... M•CORE processor if vectored interrupts are required. If the fast interrupt signal is asserted, then the vector number is determined by the highest priority fast interrupt. Technical Data 168 Interrupt Controller Module For More Information On This Product, Go to: www.freescale.com MMC2107 – Rev. 2.0 MOTOROLA ...
Page 169
... If multiple interrupt sources share the same priority level, then the interrupt service routine to determine the correct source of the interrupt. MMC2107 – Rev. 2.0 MOTOROLA For More Information On This Product, Interrupt Controller Module Go to: www.freescale.com Interrupt Controller Module Functional Description Technical Data 169 ...
Page 170
... Fixed exceptions (including autovectors) Vectored interrupts 32– lowest priority 63 = highest priority Vectored interrupts 64– lowest priority 95 = highest priority 96–127 Vectored interrupts (not used) Interrupt Controller Module For More Information On This Product, Go to: www.freescale.com Interrupt Vector Bits 6 Table 7-5. Interrupt Vector Bits 6 MMC2107 – ...
Page 171
... MMC2107 – Rev. 2.0 MOTOROLA For More Information On This Product, M•CORE processor Interrupt controller Local interrupt sources Interrupt Controller Module Go to: www.freescale.com Interrupt Controller Module Functional Description Technical Data 171 ...
Page 172
... Write SCIDRL after reading TDRE = 1 Write SCIDRL after reading Read SCIDRL after reading RDRF = 1 Read SCIDRL after reading Read SCIDRL after reading IDLE = 1 Interrupt Controller Module For More Information On This Product, Go to: www.freescale.com Flag Clearing Mechanism MMC2107 – Rev. 2.0 MOTOROLA ...
Page 173
... Write PIF = 1 or write PMR Write PIF = 1 or write PMR Write EPF0 = 1 Write EPF1 = 1 Write EPF2 = 1 Write EPF3 = 1 Write EPF4 = 1 Write EPF5 = 1 Write EPF6 = 1 Write EPF7 = 1 Interrupt Controller Module Go to: www.freescale.com Interrupt Controller Module Functional Description Flag Clearing Mechanism Technical Data 173 ...
Page 174
... Freescale Semiconductor, Inc. Interrupt Controller Module Technical Data 174 Interrupt Controller Module For More Information On This Product, Go to: www.freescale.com MMC2107 – Rev. 2.0 MOTOROLA ...
Page 175
... Fixed address space Byte, half-word (16-bit), or word (32-bit) read/write accesses One clock per access (including bytes, half-words, and words) Supervisor or user mode access Standby power supply switch to support an external power supply Static Random-Access Memory (SRAM) Go to: www.freescale.com ) . . . . . . . . . . . . . . . . . . . . 176 STBY Technical Data 175 ...
Page 176
... STBY . The value of the capacitor, C, can be calculated as transition near the voltage switch DD voltage. STBY Static Random-Access Memory (SRAM) For More Information On This Product, Go to: www.freescale.com ) provides standby voltage to the nodes the standby voltage STBY is below the voltage below the DD ...
Page 177
... SRAM contents. 8.8 Interrupts The SRAM module does not generate interrupt requests. MMC2107 – Rev. 2.0 MOTOROLA For More Information On This Product, Static Random-Access Memory (SRAM) Go to: www.freescale.com Static Random-Access Memory (SRAM) Reset Operation Technical Data 177 ...
Page 178
... Freescale Semiconductor, Inc. Static Random-Access Memory (SRAM) Technical Data 178 Static Random-Access Memory (SRAM) For More Information On This Product, Go to: www.freescale.com MMC2107 – Rev. 2.0 MOTOROLA ...
Page 179
... Master Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 Register Read and Write Operation . . . . . . . . . . . . . . . . . . 205 Array Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 Program Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Program Margin Reads . . . . . . . . . . . . . . . . . . . . . . . . . 211 Programming Shadow Information 212 Program Pulse-Width and Amplitude Modulation . . . . . 213 Overprogramming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 Non-Volatile Memory FLASH (CMFR) Go to: www.freescale.com Technical Data 179 ...
Page 180
... Erasing Shadow Information Words 219 Erase Pulse Amplitude and Width Modulation . . . . . . . . . . 219 Emulation Operation 220 Master Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220 Interrupts 220 Non-Volatile Memory FLASH (CMFR) For More Information On This Product, Go to: www.freescale.com . The program and PP Figure 9-1. MMC2107 – Rev. 2.0 MOTOROLA ...
Page 181
... Programming: – Program up to 512 bytes at a time – Simultaneously program up to eight 64-byte pages located at the same block offset address External V program and erase power supply PP Non-Volatile Memory FLASH (CMFR) Go to: www.freescale.com Non-Volatile Memory FLASH (CMFR) Features Technical Data 181 ...
Page 182
... CMFR. For details of the CMFR module configuration register (CMFRMCR) see 9.7.1.1 CMFR Module Configuration Register High-Voltage Control Technical Data 182 Register. Non-Volatile Memory FLASH (CMFR) For More Information On This Product, Go to: www.freescale.com and 9.7.1.3 CMFR MMC2107 – Rev. 2.0 MOTOROLA ...
Page 183
... AND SHADOW INFORMATION 64-BYTE PROGRAM PAGE BUFFER 0 BUS INTERFACE UNIT (BIU) Figure 9-1. CMFR 128-Kbyte Block Diagram and 9.8.3 Array Read Non-Volatile Memory FLASH (CMFR) Go to: www.freescale.com Non-Volatile Memory FLASH (CMFR) Block Diagram 0x0001_c000—0x0001_ffff 0x0001_8000—0x0001_bfff 0x0001_4000—0x0001_7fff 0x0001_0000—0x0001_3fff 0x0000_c000— ...
Page 184
... CMFR array. The shadow information is in the lowest array block 0 of the CMFR array. Note that the shadow row is erased with block 0. Technical Data 184 Non-Volatile Memory FLASH (CMFR) For More Information On This Product, Go to: www.freescale.com , to PP MMC2107 – Rev. 2.0 MOTOROLA ...
Page 185
... All CMFR array off-page reads between the first programming write and clearing the SES bit are program margin reads. MMC2107 – Rev. 2.0 MOTOROLA For More Information On This Product, Non-Volatile Memory FLASH (CMFR) Go to: www.freescale.com Non-Volatile Memory FLASH (CMFR) Glossary of Terms Technical Data 185 ...
Page 186
... Technical Data 186 FLASH CONTROL 32 BYTES CMFR FLASH 128 KBYTES Figure 9-2. CMFR Array and Control Register Addressing Non-Volatile Memory FLASH (CMFR) For More Information On This Product, Go to: www.freescale.com Figure 9-2. 0x00d0_001f UNIMPLEMENTED 0x00d0_000c 0x00d0_000b CMFR HIGH-VOLTAGE CONTROL REGISTER (CMFRCTL) 0x00d0_0008 ...
Page 187
... Table 9-1. Non-Volatile Memory FLASH Memory Map Control Register Located in Supervisor Data Space Module configuration register (CMFRMCR) Module test register (CMFRMTR) High-voltage control register (CMFRCTL) Non-Volatile Memory FLASH (CMFR) Go to: www.freescale.com Non-Volatile Memory FLASH (CMFR) Registers and Memory Map Unimplemented Technical Data 187 ...
Page 188
... SUPV6 SUPV5 SUPV4 DATA6 DATA5 DATA4 Writes have no effect and the access terminates without a transfer error exception. Non-Volatile Memory FLASH (CMFR) For More Information On This Product, Go to: www.freescale.com Bit 24 SIE LOCKCTL DIS RSVD24 0 0 Note Bit 16 SUPV3 SUPV2 SUPV1 SUPV0 ...
Page 189
... Debug mode disabled 1 = Emulation mode enabled 0 = Emulation mode disabled 1 = Shadow information enabled; normal array access disabled 0 = Shadow information disabled; normal array access enabled Non-Volatile Memory FLASH (CMFR) Go to: www.freescale.com Non-Volatile Memory FLASH (CMFR) Registers and Memory Map 9.8.7 Emulation Technical Data 189 ...
Page 190
... The reset value is defined during reset configuration by the external D28 pin. Technical Data 190 1 = Write-locked registers protected 0 = Write-lock disabled 1 = Array information disabled 0 = Array information enabled Non-Volatile Memory FLASH (CMFR) For More Information On This Product, Go to: www.freescale.com MMC2107 – Rev. 2.0 MOTOROLA ...
Page 191
... For More Information On This Product Array block in supervisor address space 0 = Array block in unrestricted address space 1 = Array block in data address space 0 = Array block is both data and program address space Non-Volatile Memory FLASH (CMFR) Go to: www.freescale.com Non-Volatile Memory FLASH (CMFR) Registers and Memory Map Technical Data 191 ...
Page 192
... If the LOCKCTL bit is set before PROTECT[7:0] is cleared, the device must use debug mode to program or erase the CMFR. Technical Data 192 1 = Array block protected 0 = Array block not protected Non-Volatile Memory FLASH (CMFR) For More Information On This Product, Go to: www.freescale.com MMC2107 – Rev. 2.0 MOTOROLA ...
Page 193
... For More Information On This Product, Bit Bit Bit Bit RSVD6 GDB Writes have no effect and the access terminates without a transfer error exception. Non-Volatile Memory FLASH (CMFR) Go to: www.freescale.com Non-Volatile Memory FLASH (CMFR) Registers and Memory Map Bit Bit Bit 8 NVR PAWS2 PAWS1 PAWS0 Bit ...
Page 194
... Negative voltage high range Table 9-2. Negative Voltage Modulation PAWS[2:0] 100 101 110 111 0XX 1. When PAWS[ and PAWS[1:0] have no effect. 9-2. Non-Volatile Memory FLASH (CMFR) For More Information On This Product, Go to: www.freescale.com NVR = 0 NVR = 1 –6 V –2 V –7 V –3 V –8 V –4 V –9 V –5 V (1) Reserved MMC2107 – ...
Page 195
... MMC2107 – Rev. 2.0 MOTOROLA For More Information On This Product Gate selected 0 = Drain/source selected Table 9-3. Drain Amplitude Modulation (GDB = 0) PAWS[2:0] 100 101 110 111 Non-Volatile Memory FLASH (CMFR) Go to: www.freescale.com Non-Volatile Memory FLASH (CMFR) Registers and Memory Map Drain Voltage ...
Page 196
... Bit RSVD6 Writes have no effect and the access terminates without a transfer error exception. Figure 1 = Pulse applied to array or CMFR in recovery 0 = Pulse not applied to array Non-Volatile Memory FLASH (CMFR) For More Information On This Product, Go to: www.freescale.com SCLKR0 CLKPE1 CLKPE0 CLKPM3 CLKPM2 CLKPM1 CLKPM0 ...
Page 197
... MMC2107 – Rev. 2.0 MOTOROLA For More Information On This Product, PULSE WIDTH Figure 9-6. Pulse Status Timing pulse width = system clock period Table 9-4) Non-Volatile Memory FLASH (CMFR) Go to: www.freescale.com Non-Volatile Memory FLASH (CMFR) Registers and Memory Map RECOVERY 10) Technical Data ...
Page 198
... Table 9-4. System Clock Range System Clock Frequency (MHz) Minimum 000 001 8 010 12 011 18 100 24 101 36 Reserved by Motorola for future use Non-Volatile Memory FLASH (CMFR) For More Information On This Product, Go to: www.freescale.com Clock Scaling (R) (1) Maximum Reserved 3 Table 9-4 to set MMC2107 – Rev. 2.0 ...
Page 199
... Pulse Width Range for all System Clock Frequencies from 8.0 MHz to 33.0 MHz Minimum Non-Volatile Memory FLASH (CMFR) Go to: www.freescale.com Non-Volatile Memory FLASH (CMFR) Registers and Memory Map 10] 9-5. (1) Maximum N 1.25E – 128 8.33E – 8 4.00 s 0.34 ms 8.00 s 0.68 ms 16.00 s 1.36 ms 32.0 s 2.73 ms 4.096 ms 349 ...
Page 200
... (CLKPM[6:0]) and solving for CLKPM[6:0] yields 42. Check the results — pulse width = 30.3 ns SCLKR[2:0] = 100, CLKPE[1:0] = 11, CLKPM[6:0] = 0101010, ERASE = 0, system clock frequency = 33.0 MHz Non-Volatile Memory FLASH (CMFR) For More Information On This Product, Go to: www.freescale.com shows that a SCLKR[2:0] value of 100 shows that when ...