MMCCMB2107 Freescale, MMCCMB2107 Datasheet - Page 446

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MMCCMB2107

Manufacturer Part Number
MMCCMB2107
Description
Manufacturer
Freescale
Datasheet

Specifications of MMCCMB2107

Lead Free Status / RoHS Status
Not Compliant
Queued Analog-to-Digital Converter (QADC)
18.9.2.3 External Multiplexed Address Configuration
18.9.3 Analog Subsystem
18.9.3.1 Analog-to-Digital Converter Operation
18.9.3.2 Conversion Cycle Times
Technical Data
446
NOTE:
The QADC can drive external multiplexed addresses. If configured to
drive external addresses, the external address pins MA[1:0] will function
as address pins and will not maintain analog input functions in external
address mode.
This section describes the QADC analog subsystem, which includes the
front-end analog multiplexer and analog-to-digital converter.
The analog subsystem consists of the path from the input pins to the A/D
converter block. Signals from the queue control logic are fed to the
multiplexer and state machine. The end-of-conversion (EOC) signal and
the successive-approximation register (SAR) reflect the result of the
conversion.
subsystem.
The following description assumes the use of a buffer amplifier.
Total conversion time is made up of initial sample time, final sample time,
and resolution time. Initial sample time refers to the time during which the
selected input channel is coupled through the buffer amplifier to the
sample capacitor. This buffer is used to quickly reproduce its input signal
on the sample capacitor and minimize charge sharing errors. During the
final sampling period the amplifier is bypassed, and the multiplexer input
charges the sample capacitor array directly for improved accuracy.
During the resolution period, the voltage in the sample capacitor is
converted to a digital value and stored in the SAR.
Initial sample time is fixed at two QCLK cycles. Final sample time can be
2, 4, 8, or 16 QCLK cycles, depending on the value of the IST field in the
CCW. Resolution time is 10 QCLK cycles.
Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
Figure 18-19
Go to: www.freescale.com
shows a block diagram of the QADC analog
MMC2107 – Rev. 2.0
MOTOROLA