MMCCMB2107 Freescale, MMCCMB2107 Datasheet - Page 81

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MMCCMB2107

Manufacturer Part Number
MMCCMB2107
Description
Manufacturer
Freescale
Datasheet

Specifications of MMCCMB2107

Lead Free Status / RoHS Status
Not Compliant
MMC2107 – Rev. 2.0
MOTOROLA
Timer 1 (TIM1) and Timer 2 (TIM2)
Note: Addresses for TIM1 are at 0x00ce_#### and addresses for TIM2 are at 0x00cf_####.
P = Current pin state
0x00ce_0000
0x00ce_0001
0x00ce_0002
0x00ce_0003
0x00ce_0004
0x00ce_0005
0x00ce_0006
0x00cf_0000
0x00cf_0001
0x00cf_0002
0x00cf_0003
0x00cf_0004
0x00cf_0005
0x00cf_0006
Address
Data Register (TIMOC3D)
Timer Output Compare 3
Timer Output Compare 3
Output Compare Select
Timer Counter Register
Timer Counter Register
Register (TIMCFORC)
Register 1 (TIMSCR1)
Timer Compare Force
Timer System Control
Register Name
Timer Input Capture/
Register (TIMIOS)
High (TIMCNTH)
U = Unaffected
Low (TIMCNTL)
See page 300.
See page 301.
See page 302.
See page 303.
See page 304.
See page 304.
See page 305.
Mask Register
(TIMOC3M)
Figure 2-2. Register Summary (Sheet 28 of 34)
Freescale Semiconductor, Inc.
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TIMEN
Bit 15
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
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0
0
0
0
0
0
0
0
0
0
0
System Memory Map
= Writes have no effect and the access terminates without a transfer error exception.
14
6
0
0
6
0
0
6
0
0
6
0
0
6
0
6
0
6
0
0
6
13
5
0
0
5
0
0
5
0
0
5
0
0
5
0
5
5
0
5
0
0
TFFCA
12
4
0
0
4
0
0
4
0
0
4
0
0
4
0
4
4
0
4
0
Bit Number
OC3M3
OC3D3
FOC3
IOS3
11
3
0
3
0
0
3
0
3
0
3
0
3
3
0
3
0
0
OC3M2
OC3D2
FOC2
IOS2
10
2
0
2
0
0
2
0
2
0
2
0
2
2
0
2
0
0
System Memory Map
OC3M1
OC3D1
FOC1
IOS1
Technical Data
1
0
1
0
0
1
0
1
0
1
0
1
0
1
0
0
9
1
Register Map
OC3M0
OC3D0
FOC0
IOS0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 8
Bit 0
Bit 0
Bit 0
0
0
0
0
0
0
0
0
0
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