MMCCMB2107 Freescale, MMCCMB2107 Datasheet - Page 392

• Manufacturer Part Number: MMCCMB2107
• Manufacturer: Freescale

Specifications of MMCCMB2107

• Lead Free Status / RoHS Status: Not Compliant

Serial Peripheral Interface Module (SPI)
Technical Data
392
The synchronized SS signal is synchronized to the SPI clock.
Figure 17-13
a full SPI clock cycle late. While the synchronized SS of the slave is high,
writing is allowed even though the SS pin is already low. The write can
change the MISO pin while the master is sampling the MISO line. The
first bit of the transfer may not be stable when the master samples it, so
the byte sent to the master may be corrupted.
Also, if the slave generates a late write, its state machine may not have
time to reset, causing it to incorrectly receive a byte from the master.
This error is most likely when the SCK frequency is half the slave SPI
clock frequency. At other baud rates, the SCK skew is no more than one
SPI clock, and there is more time between the synchronized SS signal
and the first SCK edge. For example, with a SCK frequency one-fourth
Figure 17-13. Transmission Error Due to Master/Slave Clock Skew
Freescale Semiconductor, Inc.
For More Information On This Product,
Serial Peripheral Interface Module (SPI)
Go to: www.freescale.com
shows an example with the synchronized SS signal almost
SS SYNCHRONIZED
SCK (CPOL = 0)
SCK (CPOL = 1)
TO SPI CLOCK
MOSI/MISO
CHANGE O
CHANGE O
SPI CLOCK
SAMPLE I
MOSI PIN
MISO PIN
SS PIN (I)
MISO PIN
SPIDR WRITE
THIS CYCLE
MMC2107 – Rev. 2.0
MOTOROLA