MMCCMB2107 Freescale, MMCCMB2107 Datasheet - Page 243

• Manufacturer Part Number: MMCCMB2107
• Manufacturer: Freescale

Specifications of MMCCMB2107

• Lead Free Status / RoHS Status: Not Compliant

10.8.5 Clock Operation During Reset
10.8.6 PLL Operation
MMC2107 – Rev. 2.0
MOTOROLA
In external clock mode, the system is static and does not recognize reset
until a clock is applied to EXTAL.
In PLL mode, the PLL operates in self-clocked mode (SCM) during reset
until the input reference clock to the PLL begins operating within the
limits given in the electrical specifications.
If a PLL failure causes a reset, the system enters reset using the
reference clock. Then the clock source changes to the PLL operating in
SCM. If SCM is not functional, the system becomes static. Alternately, if
the LOCEN bit in SYNCR is clear when the PLL fails, the system
becomes static. If external reset is asserted, the system cannot enter
reset unless the PLL is capable of operating in SCM.
In PLL mode, the PLL synthesizes the system clocks. The PLL can
multiply the reference clock frequency by 2x to 9x, provided that the
system clock (CLKOUT) frequency remains within the range listed in
electrical specifications. For example, if the reference frequency is
2 MHz, the PLL can synthesize frequencies of 4 MHz to 18 MHz. In
addition, the RFD can reduce the system frequency by dividing the
output of the PLL. The RFD is not in the feedback loop of the PLL, so
changing the RFD divisor does not affect PLL operation.
Figure 10-8
with example component values. Actual component values depend on
crystal specifications.
Freescale Semiconductor, Inc.
For More Information On This Product,
shows the external support circuitry for the crystal oscillator
Go to: www.freescale.com
Clock Module
Functional Description
Technical Data
Clock Module
243