MMCCMB2107 Freescale, MMCCMB2107 Datasheet - Page 489

• Manufacturer Part Number: MMCCMB2107
• Manufacturer: Freescale

Specifications of MMCCMB2107

• Lead Free Status / RoHS Status: Not Compliant

MMC2107 – Rev. 2.0
MOTOROLA
CWPQ1
Q1 RES
TRIG1
QCLK
CWP
EOC
CONVERSION TIME
QS
Figure 18-47. External Positive Edge Trigger Mode Timing With Pause
Š 14 QCLKS
LAST
0
LAST
A time separator is provided between the triggers and the end of
conversion (EOC). The relationship to QCLK displayed is not
guaranteed.
CWPQ1 and CWPQ2 typically lag CWP and only match CWP when the
associated queue is inactive. Another way to view CWPQ1(2) is that
these registers update when EOC triggers the result register to be
written.
In the case with the pause bit set (CCW0), CWP does not increment until
triggered. In the case with the pause bit clear (CCW1), the CWP
increments with the EOC.
The conversion results Q1 Res(x) show the result associated with
CCW(x). So that R0 represents the result associated with CCW0.
Freescale Semiconductor, Inc.
8
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
TIME BETWEEN
Go to: www.freescale.com
TRIGGERS
CCW0
4
CCW0
R0
Queued Analog-to-Digital Converter (QADC)
Pin Connection Considerations
CCW1
CONVERSION TIME
Š 14 QCLKS
8
CCW2
CCW1
Technical Data
R1
489