MMCCMB2107 Freescale, MMCCMB2107 Datasheet - Page 105

• Manufacturer Part Number: MMCCMB2107
• Manufacturer: Freescale

Specifications of MMCCMB2107

• Lead Free Status / RoHS Status: Not Compliant

3.8.4 Output Pad Strength Configuration
3.8.5 Clock Mode Selection
MMC2107 – Rev. 2.0
MOTOROLA
External clock mode; PLL disabled
1:1 PLL mode
Normal PLL mode; external clock reference
Normal PLL mode; crystal oscillator reference
1. Modifying the default configurations is possible only if the external RCON pin is asserted low.
Clock Mode
Output pad strength is determined during reset configuration as shown
in
can be changed by programming the LOAD bit of the chip configuration
register.
The clock mode is selected during reset and reflected in the PLLMODE,
PLLSEL, and PLLREF bits of SYNSR. Once reset is exited, the clock
mode cannot be changed.
Table 3-12
Output pads configured for default strength
Output pads configured for full strength
1. Modifying the default configurations is possible only if the external RCON pin is asserted
Table
Freescale Semiconductor, Inc.
low.
Table 3-12. Clock Mode Selection
For More Information On This Product,
Optional Pin Function Selection
Table 3-11. Output Pad Driver Strength Selection
3-11. Once reset is exited, the output pad strength configuration
Chip Configuration Module (CCM)
summarizes clock mode selection during reset configuration.
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V
V
V
V
DDSYN
DDSYN
DDSYN
DDSYN
MODE Bit
driven high
driven high
driven high
driven low
Synthesizer Status Register (SYNSR)
D23 driven high
D23 driven high
D23 driven low
D23 don’t care
(1)
PLLSEL Bit
Chip Configuration Module (CCM)
CCR Register LOAD Bit
D21 driven low
D2 driven high
Functional Description
D22 driven high
D22 driven low
D22 don’t care
D22 don’t care
PLLREF Bit
Technical Data
(1)
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