MMCCMB2107 Freescale, MMCCMB2107 Datasheet - Page 377

• Manufacturer Part Number: MMCCMB2107
• Manufacturer: Freescale

Specifications of MMCCMB2107

• Lead Free Status / RoHS Status: Not Compliant

MMC2107 – Rev. 2.0
MOTOROLA
NOTE:
NOTE:
MSTR — Master Bit
CPOL — Clock Polarity Bit
CPHA — Clock Phase Bit
SSOE — Slave Select Output Enable Bit
Setting the SSOE bit disables the mode fault detect function.
LSBFE — LSB-First Enable Bit
In SPIDR, the MSB is always bit 7 regardless of the LSBFE bit.
The MSTR bit selects SPI master mode or SPI slave mode operation.
Reset clears MSTR.
The CPOL bit selects an inverted or non-inverted SPI clock. To
transmit data between SPI modules, the SPI modules must have
identical CPOL values. Reset clears CPOL.
The CPHA bit delays the first edge of the SCK clock. Reset sets
CPHA.
The SSOE bit and the DDRSP3 bit configure the SS pin as a
general-purpose input or a slave-select output. Reset clears SSOE.
The LSBFE enables data to be transmitted LSB first. Reset clears
LSBFE.
Freescale Semiconductor, Inc.
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1 = Master mode
0 = Slave mode
1 = Active-low clock; SCK idles high
0 = Active-high clock; SCK idles low
1 = First SCK edge at start of transmission
0 = First SCK edge 1/2 cycle after start of transmission
1 = Data transmitted LSB first.
0 = Data transmitted MSB first
Serial Peripheral Interface Module (SPI)
DDRSP3 SSOE
0
0
1
1
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Table 17-3. SS Pin I/O Configurations
0
1
0
1
Mode-fault input
General-purpose input
General-purpose output
Slave-select output
Master Mode
Serial Peripheral Interface Module (SPI)
Memory Map and Registers
Slave-select input
Slave-select input
Slave-select input
Slave-select input
Slave Mode
Technical Data
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