MMCCMB2107 Freescale, MMCCMB2107 Datasheet - Page 228

• Manufacturer Part Number: MMCCMB2107
• Manufacturer: Freescale

Specifications of MMCCMB2107

• Lead Free Status / RoHS Status: Not Compliant

Clock Module
Technical Data
228
NOTE:
NOTE:
MFD[2:0] — Multiplication Factor Divider Field
In external clock mode, the MFD[2:0] bits have no effect.
See
LOCRE — Loss of Clock Reset Enable Bit
In external clock mode, the LOCRE bit has no effect.
1. f
2. Default value out of reset
MFD[2:0] contain the binary value of the divider in the PLL feedback
loop. See
applied to the reference frequency. When MFD[2:0] are changed or
the PLL is disabled in stop mode, the PLL loses lock. In 1:1 PLL
mode, MFD[2:0] are ignored, and the multiplication factor is one.
The LOCRE bit determines how the system handles a loss of clock
condition. When the LOCEN bit is clear, LOCRE has no effect. If the
LOCS flag in SYNSR indicates a loss of clock condition, setting the
LOCRE bit causes an immediate reset. To prevent an immediate
reset, the LOCRE bit must be cleared before entering stop mode with
the PLL disabled.
Freescale Semiconductor, Inc.
sys
000 ( 1)
001 ( 2)
010 ( 4)
011 ( 8)
100 ( 16)
101 ( 32)
110 ( 64)
111 ( 128)
Table
Table 10-3. System Frequency Multiplier of the Reference
For More Information On This Product,
1 = Reset on loss of clock
0 = No reset on loss of clock
= f
ref
x (MFD + 2)/2
10-6.
(2)
Go to: www.freescale.com
Table
1/16
1/32
1/64
(2x)
000
Frequency
1/2
1/4
1/8
Clock Module
2
1
10-3. The MFD[2:0] value is the multiplication factor
RFD
3/128
3/16
3/32
3/64
001
(3x)
3/2
3/4
3/8
3
(1)
1/16
1/32
(4x)
010
1/2
1/4
1/8
in Normal PLL Mode
4
2
1
5/128
5/16
5/32
5/64
(5x)
011
5/2
5/4
5/8
MFD[2:0]
5
3/16
3/32
3/64
(6x)
100
3/2
3/4
3/8
6
3
7/128
7/16
7/32
7/64
(7x)
101
7/2
7/4
7/8
7
MMC2107 – Rev. 2.0
1/16
(8x)
110
1/2
1/4
1/8
8
4
2
1
MOTOROLA
9/128
9/16
9/32
9/64
(9x)
111
9/2
9/4
9/8
9