EP9312-CB Cirrus Logic Inc, EP9312-CB Datasheet - Page 804
![System-on-Chip Processor](/photos/12/23/122390/mfg_ep9312_series_sml.jpg)
EP9312-CB
Manufacturer Part Number
EP9312-CB
Description
System-on-Chip Processor
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets
1.EP9307-CRZ.pdf
(824 pages)
2.EP9312-IBZ.pdf
(4 pages)
3.EP9312-CB.pdf
(62 pages)
4.EP9312-CB.pdf
(17 pages)
Specifications of EP9312-CB
Peak Reflow Compatible (260 C)
No
A/d Converter
12 Bits
Leaded Process Compatible
No
No. Of I/o Pins
65
Package / Case
352-BGA
Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Other names
598-1257
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP9312-CB
Manufacturer:
CIRRUS
Quantity:
20 000
- EP9307-CRZ PDF datasheet
- EP9312-IBZ PDF datasheet #2
- EP9312-CB PDF datasheet #3
- EP9312-CB PDF datasheet #4
- Current page: 804 of 824
- Download datasheet (13Mb)
28
GPIOxEOI
GPIOxDB
28-14
GPIO Interface
EP93xx User’s Guide
31
15
31
15
Address:
Definition:
Bit Descriptions:
Address:
Definition:
In order to clear an edge sensitive interrupt that can occur over port A/B/F, the user must
write a data value of “1” to the corresponding bit in the GPIOxEOI register bit. The user must
clear an interrupt before changing Port A/B/F from interrupt mode to GPIO mode as the
interrupts are cleared once this change has occurred. Once an interrupt has occurred and the
interrupt service routine has started, one of the first instructions should be a write to this
location in order to clear the interrupt so that subsequent interrupts on the same line are not
missed.
For each port, if interrupts are enabled, it is possible to debounce the input signal. Setting a
bit in this register enables debouncing for the corresponding interrupt signal; clearing the bit
disables debouncing. Debouncing is implemented by passing the input signal through a 2-bit
shift register clocked by a 128 Hz clock.
30
14
30
14
29
13
29
13
28
12
28
12
RSVD
RSVD
GPIOAEOI: 0x8084_0098 - Write Only
GPIOBEOI: 0x8084_00B4 - Write Only
GPIOFEOI: 0x8084_0054 - Write Only
RSVD:
PxINTC:
GPIOADB: 0x8084_00A8 - Read/Write
GPIOBDB: 0x8084_00C4 - Read/Write
GPIOFDB: 0x8084_0064 - Read/Write
27
27
11
11
26
10
26
10
25
25
9
9
Copyright 2007 Cirrus Logic
Reserved. Unknown During Read.
Clears Interrupts
24
24
8
8
RSVD
RSVD
23
23
7
7
22
22
6
6
21
21
5
5
20
20
4
4
PxINTDB
PxINTC
19
19
3
3
18
18
2
2
17
17
1
1
DS785UM1
16
16
0
0
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