EP9312-CB Cirrus Logic Inc, EP9312-CB Datasheet - Page 682

• Manufacturer Part Number: EP9312-CB
• Description: System-on-Chip Processor
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-CB

• Peak Reflow Compatible (260 C): No
• A/d Converter: 12 Bits
• Leaded Process Compatible: No
• No. Of I/o Pins: 65
• Package / Case: 352-BGA
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1257

21
I
I2STXClkCfg
21-26
2
I
EP93xx User’s Guide
2
S Configuration and Status Register Descriptions
S Controller
31
15
Address:
Default
Definition:
Bit Descriptions:
30
14
29
13
28
12
0x8082_0000 - Read/Write
0x0000_0000
Transmitter clock configuration register.
RSVD:
i2s_tx_bcr:
i2s_tx_nbcg:
RSVD
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Reserved. Unknown During Read.
Defines the TX bit clock rate.
00 - I2STXClkCfg[4] defines the bit clock generation.
01 - Bit clock rate is fixed at 32x. Word length is ignored.
10 - Bit clock rate is fixed at 64x. Word length is ignored.
11 - Bit clock rate is fixed at 128x. Word length is ignored.
Defines TX not bit clock gating mode.
If I2STXClkCfg[5:6] = 00, this bit defines the bit clock rate,
otherwise ignored.
Bit clock rate = 32x if word length is 16.
Bit clock rate = 64x if word length is 32.
Bit clock rate = 64x if word length is 24.
There is a special case when the word length is 24.
If this bit = 0 and the word length is 24, the last 8 cycles
are gated off in each word.
If this bit = 1 and the word length is 24, the last 8 cycles
are not gated off in each word.
24
8
RSVD
23
7
22
6
i2s_tx_bcr
21
5
i2s_tx_nbcg
20
4
i2s_mstr
19
3
i2s_trel
18
2
i2s_tckp
17
1
DS785UM1
i2s_tlrs
16
0