EP9312-CB Cirrus Logic Inc, EP9312-CB Datasheet - Page 239
![System-on-Chip Processor](/photos/12/23/122390/mfg_ep9312_series_sml.jpg)
EP9312-CB
Manufacturer Part Number
EP9312-CB
Description
System-on-Chip Processor
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets
1.EP9307-CRZ.pdf
(824 pages)
2.EP9312-IBZ.pdf
(4 pages)
3.EP9312-CB.pdf
(62 pages)
4.EP9312-CB.pdf
(17 pages)
Specifications of EP9312-CB
Peak Reflow Compatible (260 C)
No
A/d Converter
12 Bits
Leaded Process Compatible
No
No. Of I/o Pins
65
Package / Case
352-BGA
Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Other names
598-1257
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP9312-CB
Manufacturer:
CIRRUS
Quantity:
20 000
- EP9307-CRZ PDF datasheet
- EP9312-IBZ PDF datasheet #2
- EP9312-CB PDF datasheet #3
- EP9312-CB PDF datasheet #4
- Current page: 239 of 824
- Download datasheet (13Mb)
PixelMode
DS785UM1
TRBSW
31
15
Address: 0x8003_0054
Default: 0x0000_0000
Definition: Pixel Mode register
Bit Descriptions:
DSCAN
30
14
29
13
28
12
RSVD:
0:
TRBSW:
DSCAN:
C
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
This field should be written with a value that specifies the
number of words that the FIFO empties before the FIFO
requests that it be refilled. Values greater than 16 should
be used with extreme caution as they can cause the
Raster Engine to underflow, causing video jitter or other
visual defects.
Reserved - Unknown during read
Must be written as ‘0’
Two and Two-Thirds Red/Blue Swap - Read/Write
Writing a Two and two-thirds Red/Blue Swap value to this
bit selects the ordering of Red and Blue pixels for data
shifted displays:
0 - Normal: Blue is the low order bits followed by green
and red
1 - Reverse: Red is low order bits followed by green and
blue
Dual Scan - Read/Write
Raster Engine With Analog/LCD Integrated Timing and Interface
RSVD
24
8
M
23
7
22
6
21
5
20
S
4
19
3
EP93xx User’s Guide
18
2
17
P
1
16
7-57
0
0
7
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