EP9312-CB Cirrus Logic Inc, EP9312-CB Datasheet - Page 455
![System-on-Chip Processor](/photos/12/23/122390/mfg_ep9312_series_sml.jpg)
EP9312-CB
Manufacturer Part Number
EP9312-CB
Description
System-on-Chip Processor
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets
1.EP9307-CRZ.pdf
(824 pages)
2.EP9312-IBZ.pdf
(4 pages)
3.EP9312-CB.pdf
(62 pages)
4.EP9312-CB.pdf
(17 pages)
Specifications of EP9312-CB
Peak Reflow Compatible (260 C)
No
A/d Converter
12 Bits
Leaded Process Compatible
No
No. Of I/o Pins
65
Package / Case
352-BGA
Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Other names
598-1257
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP9312-CB
Manufacturer:
CIRRUS
Quantity:
20 000
- EP9307-CRZ PDF datasheet
- EP9312-IBZ PDF datasheet #2
- EP9312-CB PDF datasheet #3
- EP9312-CB PDF datasheet #4
- Current page: 455 of 824
- Download datasheet (13Mb)
HcCommandStatus
DS785UM1
31
15
Address:
Default:
Definition:
Bit Descriptions:
30
14
29
13
28
12
RWE:
0x8002_0008
0x0000_0000
Provides current controller status and accepts controller commands.
RSVD:
HCR:
27
11
26
10
RSVD
Copyright 2007 Cirrus Logic
25
9
RemoteWakeupEnable:
This bit is used by HCD to enable or disable the remote
wakeup feature upon the detection of upstream resume
signaling. When this bit is set and the ResumeDetected bit
in HcInterruptStatus is set, a remote wakeup is signaled to
the host system. Setting this bit has no impact on the
generation of hardware interrupt.
Reserved. Unknown During Read.
HostControllerReset:
This bit is set by HCD to initiate a software reset of HC.
Regardless of the functional state of HC, it moves to the
USBSUSPEND state in which most of the operational
registers are reset except those stated otherwise; e.g., the
InterruptRouting field of HcControl, and no Host bus
accesses are allowed. This bit is cleared by HC upon the
completion of the reset operation. The reset operation
must be completed within 10 ms. This bit, when set,
should not cause a reset to the Root Hub and no
subsequent reset signaling should be asserted to its
downstream ports.
RSVD
24
8
23
7
22
6
21
5
Universal Serial Bus Host Controller
20
4
OCR
19
3
EP93xx User’s Guide
BLF
18
2
CLF
17
1
SOC
11-15
HCR
16
0
11
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