EP9312-CB Cirrus Logic Inc, EP9312-CB Datasheet - Page 78
![System-on-Chip Processor](/photos/12/23/122390/mfg_ep9312_series_sml.jpg)
EP9312-CB
Manufacturer Part Number
EP9312-CB
Description
System-on-Chip Processor
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets
1.EP9307-CRZ.pdf
(824 pages)
2.EP9312-IBZ.pdf
(4 pages)
3.EP9312-CB.pdf
(62 pages)
4.EP9312-CB.pdf
(17 pages)
Specifications of EP9312-CB
Peak Reflow Compatible (260 C)
No
A/d Converter
12 Bits
Leaded Process Compatible
No
No. Of I/o Pins
65
Package / Case
352-BGA
Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Other names
598-1257
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP9312-CB
Manufacturer:
CIRRUS
Quantity:
20 000
- EP9307-CRZ PDF datasheet
- EP9312-IBZ PDF datasheet #2
- EP9312-CB PDF datasheet #3
- EP9312-CB PDF datasheet #4
- Current page: 78 of 824
- Download datasheet (13Mb)
3
3-8
MaverickCrunch Co-Processor
EP93xx User’s Guide
3.2.1 Example 1
3.2.1.1 Setup Code
3.2.1.2 C Code
3.2.1.3 Accessing MaverickCrunch with ARM Co-Processor Instructions
3.2.1.4 MaverickCrunch Assembly Language Instructions
3.2 Programming Examples
The examples below show two algorithms, each implemented using the standard
programming languages and the MaverickCrunch instruction set.
Section
the same operation.
Section 3.2.1.2
assembly language, accessing the MaverickCrunch with ARM co-processor instructions.
Section 3.2.1.4
ldr
mov
str
register
ldr
to
orr
str
int num = 0;
for(num=0; num < 10; num++)
3.2.1.2,
num = num * 5;
loop
ldc p5, c0, [r0, #0x0]
ldc p5, c1, [r0, #0x4]
ldc p5, c2, [r0, #0x8]
ldc p5, c3, [r0, #0xc]
cdp p5, 1, c0, c0, c3, 0
cdp p5, 3, c0, c0, c2, 6
mrc p5, 0, r15 c0, c1, 4
blt loop
stc p5, c0, [r0, #0x0]
cfldr32 c0, [r0, #0x0]
cfldr32 c1, [r0, #0x4]
cfldr32 c2, [r0, #0x8]
cfldr32 c3, [r0, #0xc]
r1,
shows the program implemented in C code.
uses MaverickCrunch assembly language instructions.
r1,
r0,
r1,
r1,
r1,
Section
#0xaa
Section 3.2.1.1
[r0, #0x80]
=80930000
[r0, #0xc0]
r1, #0x00800000
[r0, #0x80]
3.2.1.3, and
Copyright 2007 Cirrus Logic
shows common setup code used by all three samples.
Section 3.2.1.4
; c0 <= c0 * 5
; c0 <= c0 - 1
; c0 < 10 ?
; data section preloaded with 0x0 (“num”)
; data section preloaded with 0xa
; data section preloaded with 0x1
; data section preloaded with 0x5
;
; data section preloaded with 0x0 (“num”)
; data section preloaded with 0xa
; data section preloaded with 0x1
; data section preloaded with 0x5
; enable MaverickCrunch co-processor
no, store result
; Syscon base address
; Turn on CPENA bit in DEVCFG register
; SW lock key
; unlock by writing key to SysSWLock
;
;
show three coding samples performing
yes
Section 3.2.1.3
uses ARM
DS785UM1
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