EP9312-CB Cirrus Logic Inc, EP9312-CB Datasheet - Page 362

• Manufacturer Part Number: EP9312-CB
• Description: System-on-Chip Processor
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-CB

• Peak Reflow Compatible (260 C): No
• A/d Converter: 12 Bits
• Leaded Process Compatible: No
• No. Of I/o Pins: 65
• Package / Case: 352-BGA
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1257

9
IntStsP/IntStsC
9-60
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
RSVD
31
15
Address:
Chip Reset:
Soft Reset:
Definition:
Bit Descriptions:
RSVD
RWI
30
14
RxMI
29
13
RxBI
MIII
28
12
0x8001_0028, for IntStsP - Read/Write
0x8001_002C, for IntStsC - Read Only
0x0000_0000
0x0000_0000
Interrupt Status Preserve and Clear Registers. The interrupt status bits are set
when the corresponding events occur in the MAC. If the corresponding
interrupt enable bit is set in the interrupt enable register, an interrupt signal will
be generated.
Interrupt status is available at two different offsets: Interrupt Status Preserve
and Interrupt Status Clear. Both offsets are a read of the same storage.
Reading the Interrupt Status register Preserve has no effect on the status in
the register, but writing a 1 to a location in this register clears the status bit,
writing a zero has no effect. Reading the Interrupt Status Clear register clears
all the bits in the register that are accessed as defined by the AHB HSIZE
signal. Therefore a routine which will handle all reported status may read via
the Interrupt Status Clear thereby saving a write operation.
RSVD:
RWI:
RxSQI
PHYSI
27
11
TxLEI
26
10
TI
Copyright 2007 Cirrus Logic
AHBE
ECI
25
9
Reserved. Unknown During Read.
Remote Wake-up Interrupt. The remote wake status is set
when a remote wake-up frame is received, and the
RemoteWakeEn (RXCtl) is set. A remote wake-up frame
must pass the receive destination address filter and have
a contiguous sequence of 6 bytes of FFh followed by 8
repetitions of the Individual Address and be a legal frame
(legal length and good CRC).
TxUHI
SWI
24
8
23
7
RSVD
22
6
RSVD
21
5
OTHER
20
4
TxSQ
19
3
RxSQ
MOI
18
2
TxCOI
17
1
DS785UM1
RSVD
RxROI
16
0