EP9312-CB Cirrus Logic Inc, EP9312-CB Datasheet - Page 550

• Manufacturer Part Number: EP9312-CB
• Description: System-on-Chip Processor
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-CB

• Peak Reflow Compatible (260 C): No
• A/d Converter: 12 Bits
• Leaded Process Compatible: No
• No. Of I/o Pins: 65
• Package / Case: 352-BGA
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1257

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UART1 With HDLC and Modem Control Signals
EP93xx User’s Guide
CMAS:
TXCM:
RXCM:
TXENC:
RXENC:
SYNC:
TFCEN:
TABEN:
RFCEN:
Copyright 2007 Cirrus Logic
Clock Master:
1 - Transmitter and/or receiver use 1x clock generated by
the internal transmitter.
0 - Transmitter and/or receiver use 1x clock generated
externally.
Transmit Clock Mode.
1 - Generate 1x clock when in synchronous HDLC mode
using NRZ encoding.
0 - Do not generate clock.
This bit has no effect unless TXENC is clear and
synchronous HDLC is enabled.
Receive Clock Mode.
1 - Use external 1x clock when in synchronous HDLC
mode using NRZ encoding.
0 - Do not use external clock.
This bit has no effect unless RXENC is clear and
synchronous HDLC is enabled.
Transmit Encoding method.
1 - Use Manchester bit encoding.
0 - Use NRZ bit encoding.
This bit has no effect unless synchronous HDLC is
enabled
Receive Encoding method.
1 - Use Manchester bit encoding.
0 - Use NRZ bit encoding.
This bit has no effect unless synchronous HDLC is
enabled.
Synchronous / Asynchronous HDLC Enable.
0 - Select asynchronous HDLC for TX and RX.
1 - Select synchronous HDLC for TX and RX.
Transmit Frame Complete Interrupt Enable.
0 - TFC interrupt will not occur.
1 - TFC interrupt will occur whenever TFC bit is set.
Transmit Frame Abort Interrupt Enable.
0 - TAB interrupt will not occur.
1 - TAB interrupt will occur whenever TAB bit is set.
Receive Frame Complete Interrupt Enable.
0 - RFC interrupt will not occur.
1 - RFC interrupt will occur whenever RAB bit or EOF bit is
set.
DS785UM1