EP9312-CB Cirrus Logic Inc, EP9312-CB Datasheet - Page 222

• Manufacturer Part Number: EP9312-CB
• Description: System-on-Chip Processor
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-CB

• Peak Reflow Compatible (260 C): No
• A/d Converter: 12 Bits
• Leaded Process Compatible: No
• No. Of I/o Pins: 65
• Package / Case: 352-BGA
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1257

7
VBlankStrtStop
7-40
Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
31
15
Address: 0x8003_0228
Default: 0x0000_0000
Definition: Vertical BLANK signal Start/Stop register
Bit Descriptions:
30
14
RSVD
RSVD
29
13
28
12
RSVD:
STOP:
STRT:
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Reserved - Unknown during read
Stop - Read/Write
The STOP value is the value of the Vertical down counter
at which the VBLANKn signal becomes inactive (stops).
This is used to generate the BLANKn signal that is used
by external devices and indicates the end of the active
video portion for the Vertical frame. Please refer to video
signalling timing diagrams in
VBLANKn is an internal block signal. The NBLANK output
is a logical AND of NVBLANK and HBLANKn.
Start - Read/Write
The STRT value is the value of the Vertical down counter
at which the VBLANKn signal becomes active (starts).
This is used to generate the BLANKn signal that is used
by external devices and indicates the start of the active
video portion for the Vertical frame. Please refer to video
signalling timing diagrams in
VBLANKn is an internal block signal. The NBLANK output
is a logical AND of NVBLANK and HBLANKn.
24
8
23
7
22
6
STOP
STRT
21
5
Figure 7-9
Figure 7-9
20
4
19
3
and
and
18
2
Figure
Figure
17
1
DS785UM1
7-10.
7-10.
16
0