EP9312-CB Cirrus Logic Inc, EP9312-CB Datasheet - Page 350

• Manufacturer Part Number: EP9312-CB
• Description: System-on-Chip Processor
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-CB

• Peak Reflow Compatible (260 C): No
• A/d Converter: 12 Bits
• Leaded Process Compatible: No
• No. Of I/o Pins: 65
• Package / Case: 352-BGA
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1257

9
DiagAd
9-48
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
31
15
Address:
Chip Reset:
Soft Reset:
Definition:
Bit Descriptions:
30
14
29
13
28
12
RESET:
0x8001_0038 - Read/Write
0x0000_0000
0x0000_0000
Diagnostic Address Register. The Diagnostic Address Register provides an
indirect addressing method to point to internal diagnostic locations, which
provide access to features not required for normal driver operation. To access
the internal registers, the address of the register is written to the Diagnostic
Address register, and the Diagnostic Data register is used to access the actual
data.
RSVD:
ADDR:
RSVD
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Soft Reset. This is an act-once bit. When set, a Soft Reset
is initiated immediately, this will reset the FIFO, mac and
Descriptor Processor. This bit is cleared as a result of the
reset. Driver software should wait until the bit is cleared
before proceeding with MAC initialization.
Reserved. Unknown During Read.
Diagnostic Address. The following table identifies the
address map.
Address
0x00
0x04
0x08
0x98
0x9C
0xA0
0xA4
0xA8
0xAC
24
8
RSVD
23
7
22
6
Register Name
Debug Control
Debug FIFO Control
Debug FIFO Data
Receive Data FIFO Pointers
Transmit Data FIFO Pointers
Receive Status FIFO Pointers
Transmit Status FIFO Pointers
Receive Descriptor FIFO Pointers
Transmit Descriptor FIFO Pointers
21
5
20
4
ADDR
19
3
18
2
17
1
DS785UM1
16
0