EP9312-CB Cirrus Logic Inc, EP9312-CB Datasheet - Page 224
![System-on-Chip Processor](/photos/12/23/122390/mfg_ep9312_series_sml.jpg)
EP9312-CB
Manufacturer Part Number
EP9312-CB
Description
System-on-Chip Processor
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets
1.EP9307-CRZ.pdf
(824 pages)
2.EP9312-IBZ.pdf
(4 pages)
3.EP9312-CB.pdf
(62 pages)
4.EP9312-CB.pdf
(17 pages)
Specifications of EP9312-CB
Peak Reflow Compatible (260 C)
No
A/d Converter
12 Bits
Leaded Process Compatible
No
No. Of I/o Pins
65
Package / Case
352-BGA
Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Other names
598-1257
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP9312-CB
Manufacturer:
CIRRUS
Quantity:
20 000
- EP9307-CRZ PDF datasheet
- EP9312-IBZ PDF datasheet #2
- EP9312-CB PDF datasheet #3
- EP9312-CB PDF datasheet #4
- Current page: 224 of 824
- Download datasheet (13Mb)
7
Horizontal Frame Timing Registers
HClkTotal
HSyncStrtStop
7-42
Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
31
15
31
15
Address: 0x8003_0010
Default: 0x0000_0000
Definition: Total pixel clocks that compose a horizontal line
Bit Descriptions:
Address: 0x8003_0014
Default: 0x0000_0000
Definition: HorizontaL Sync Start/Stop Register
Bit Descriptions:
30
14
30
14
RSVD
RSVD
RSVD
29
13
29
13
28
12
28
12
RSVD:
TOTAL:
RSVD:
STOP:
27
27
11
11
26
10
26
10
Copyright 2007 Cirrus Logic
25
25
9
9
Reserved - Unknown during read
Total - Read/Write
The HClk Total timing register contains the total number of
clocks for a horizontal video line including synchronization,
blanking, and active clocks. This value is used to preset
the Horizontal down counter. Please refer to video
signalling timing diagrams in
Reserved - Unknown during read
Stop - Read/Write
24
24
8
8
RSVD
23
23
7
7
22
22
6
6
TOTAL
STOP
STRT
21
21
5
5
Figure 7-9
20
20
4
4
19
19
3
3
and
18
18
2
2
Figure
17
17
1
1
DS785UM1
7-10.
16
16
0
0
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