EP9312-CB Cirrus Logic Inc, EP9312-CB Datasheet - Page 146

• Manufacturer Part Number: EP9312-CB
• Description: System-on-Chip Processor
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-CB

• Peak Reflow Compatible (260 C): No
• A/d Converter: 12 Bits
• Leaded Process Compatible: No
• No. Of I/o Pins: 65
• Package / Case: 352-BGA
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1257

5
ClkSet2
5-20
System Controller
EP93xx User’s Guide
31
15
Address:
Definition:
Bit Descriptions:
Note: The value in the register is the actual coefficient minus one.
30
14
USB DIV
PLL2 X1FBD1
29
13
28
12
nBYP1:
SMCROM:
FCLKDIV:
0x8093_0024 - Read/Write
The ClkSet2 register is used for setting the dividers internally to PLL2 and to
the USB Host divider. The reset setting for PLL2 creates a frequency of
48 MHz. The default divider for USB_DIV is divide by 1, which will produce the
USB host clock frequency and FIR clock frequency of 48 MHz.
PLL2_X2IPD:
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
This bit selects the clock source for the processor clock
dividers. With this bit clear, the system wakes up and
boots with the PLL bypassed and uses an external clock
source. With nBYP1 set, the system runs with the PLL
generated clock. The default for this bit is to boot/run from
external clock source.
If set, this bit will gate off the HCLK to the Static Memory
Controller when in Halt mode and therefore save power.
When in Halt mode, there are no Instruction Code fetches
occurring and therefore if there are no DMA operations in
progress that may require the SMC, there will be no
accesses to this controller. It may therefore be safely
disabled when in Halt mode. This bit is 0b on reset.
These three bits set the divide ratio between the VCO
output and processor clock. On power-on-reset the value
is set to 000b.
000 - Divide by 1
001 - Divide by 2
010 - Divide by 4
For FCLKDIV values equal to 1xxb (except for 100b), the
divide ratio will be divide by 1.
These 5 register bits set the input divider for PLL2
operation. On power-on-reset the value is set to 10111b
(23 decimal).
PLL2 X2FBD2
24
8
RSVD
23
7
22
6
011 - Divide by 8
100 - Divide by 16
21
5
20
4
nBYP2
19
3
PLL2 X2IPD
PLL2_EN
18
2
17
1
DS785UM1
PLL2_PS
16
0