EP9312-CB Cirrus Logic Inc, EP9312-CB Datasheet - Page 444
![System-on-Chip Processor](/photos/12/23/122390/mfg_ep9312_series_sml.jpg)
EP9312-CB
Manufacturer Part Number
EP9312-CB
Description
System-on-Chip Processor
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets
1.EP9307-CRZ.pdf
(824 pages)
2.EP9312-IBZ.pdf
(4 pages)
3.EP9312-CB.pdf
(62 pages)
4.EP9312-CB.pdf
(17 pages)
Specifications of EP9312-CB
Peak Reflow Compatible (260 C)
No
A/d Converter
12 Bits
Leaded Process Compatible
No
No. Of I/o Pins
65
Package / Case
352-BGA
Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Other names
598-1257
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP9312-CB
Manufacturer:
CIRRUS
Quantity:
20 000
- EP9307-CRZ PDF datasheet
- EP9312-IBZ PDF datasheet #2
- EP9312-CB PDF datasheet #3
- EP9312-CB PDF datasheet #4
- Current page: 444 of 824
- Download datasheet (13Mb)
11
11-4
Universal Serial Bus Host Controller
EP93xx User’s Guide
11.2.2.2 Data Structures
The basic building blocks for communication across the interface are the Endpoint Descriptor
(ED) and Transfer Descriptor (TD).
The Host Controller Driver assigns an Endpoint Descriptor to each endpoint in the system.
The Endpoint Descriptor contains the information necessary for the Host Controller to
communicate with the endpoint. The fields include the maximum packet size, the endpoint
address, the speed of the endpoint, and the direction of data flow. Endpoint Descriptors are
linked in a list.
A queue of Transfer Descriptors is linked to the Endpoint Descriptor for the specific endpoint.
The Transfer Descriptor contains the information necessary to describe the data packets to
be transferred. The fields include data toggle information, shared memory buffer location, and
completion status codes. Each Transfer Descriptor contains information that describes one or
more data packets. The data buffer for each Transfer Descriptor ranges in size from 0 to 8192
bytes with a maximum of one physical page crossing. Transfer Descriptors are linked in a
queue: the first one queued is the first one processed.
Each data transfer type has its own linked list of Endpoint Descriptors to be processed.
Figure
The head pointers to the bulk and control Endpoint Descriptor lists are maintained within the
operational registers in the HC. The Host Controller Driver initializes these pointers prior to
the Host Controller gaining access to them. Should these pointers need to be updated, the
Host Controller Driver may need to halt the Host Controller from processing the specific list,
update the pointer, then re-enable the HC.
The head pointers to the interrupt Endpoint Descriptor lists are maintained within the HCCA.
There is no separate head pointer for isochronous transfers. The first isochronous Endpoint
Descriptor simply links to the last interrupt Endpoint Descriptor. There are 32 interrupt head
pointers. The head pointer used for a particular frame is determined by using the last 5 bits of
the Frame Counter as an offset into the interrupt array within the HCCA.
The interrupt Endpoint Descriptors are organized into a tree structure with the head pointers
being the leaf nodes. The desired polling rate of an Interrupt Endpoint is achieved by
11-3, Typical List Structure, is a representation of the data structure relationships.
Head Ptr
Figure 11-3. Typical List Structure
ED
TD
TD
TD
Copyright 2007 Cirrus Logic
ED
TD
ED
TD
TD
ED
TD
DS785UM1
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