EP9312-CB Cirrus Logic Inc, EP9312-CB Datasheet - Page 360

• Manufacturer Part Number: EP9312-CB
• Description: System-on-Chip Processor
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-CB

• Peak Reflow Compatible (260 C): No
• A/d Converter: 12 Bits
• Leaded Process Compatible: No
• No. Of I/o Pins: 65
• Package / Case: 352-BGA
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1257

9
9-58
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
Address:
Chip Reset:
Soft Reset:
Definition:
Bit Descriptions:
0x8001_0024 - Read/Write
0x0000_0000
0x0000_0000
Interrupt Enable Register
RSVD:
RWIE:
RxMIE:
RxBIE:
RxSQIE:
TxLEIE:
ECIE:
TxUHIE:
Copyright 2007 Cirrus Logic
Reserved. Unknown During Read.
Remote Wake-up Interrupt Enable. Setting this bit causes
an interrupt to be generated when a remote wake-up
frame is detected and the MAC is in the Remote Wake-up
mode (RXCtl).
Receiver Miss Interrupt Enable. When set, this bit will
cause an interrupt whenever a complete receive frame is
discarded due to lack of storage. This may be as a result
of long bus latency or insufficient receive descriptors. The
total number of missed frames is also counted in the
RxMiss Counter.
Receive Buffer Interrupt Enable. When set, this bit will
cause an interrupt to be generated when the last available
receive descriptor has been read into the MAC.
Receive Status Queue Interrupt Enable. When this bit is
set, an interrupt will be generated when the last available
status queue entry has been written (RXStsEnq = 0).
Transmit Length Error Interrupt Enable. Setting this bit
causes an interrupt to be generated when a transmit frame
equals or exceeds the length specified in the Max Frame
Length register.
End of Chain Interrupt Enable. The end of chain interrupt
is generated when the last transmit descriptor has been
loaded into the MAC. There may still be transmit
descriptors and or transmit data remaining in the MAC at
this time.
Transmit Underrun Halt Interrupt Enable. If there is a
transmission, and the MAC runs out of data before the full
transmitted length, then there is a transmit underrun. If the
MAC is programmed to halt in this condition (Bus Master
Control), setting TxUnderrunHaltiE will cause an interrupt
to be generated.
DS785UM1