EP9312-CB Cirrus Logic Inc, EP9312-CB Datasheet - Page 628
![System-on-Chip Processor](/photos/12/23/122390/mfg_ep9312_series_sml.jpg)
EP9312-CB
Manufacturer Part Number
EP9312-CB
Description
System-on-Chip Processor
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets
1.EP9307-CRZ.pdf
(824 pages)
2.EP9312-IBZ.pdf
(4 pages)
3.EP9312-CB.pdf
(62 pages)
4.EP9312-CB.pdf
(17 pages)
Specifications of EP9312-CB
Peak Reflow Compatible (260 C)
No
A/d Converter
12 Bits
Leaded Process Compatible
No
No. Of I/o Pins
65
Package / Case
352-BGA
Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Other names
598-1257
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP9312-CB
Manufacturer:
CIRRUS
Quantity:
20 000
- EP9307-CRZ PDF datasheet
- EP9312-IBZ PDF datasheet #2
- EP9312-CB PDF datasheet #3
- EP9312-CB PDF datasheet #4
- Current page: 628 of 824
- Download datasheet (13Mb)
17
MISR
17-32
IrDA
EP93xx User’s Guide
31
15
Address:
Default:
Definition:
Bit Descriptions:
30
14
29
13
28
12
0x808B_0080 - Read/Write
0x0000_0000
MIR Status Register.
RSVD:
RFL:
RIL:
RFC:
RSVD
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Reserved. Unknown During Read.
Receive Frame Lost. Set to a “1” when a ROR occurred at
the start of a new frame, before any data for the frame
could be put into the receive FIFO. This bit is cleared by
writing a “1” to this bit. This occurs if the last entry in the
FIFO already contains a valid EOF bit from a previous
frame when a FIFO overrun occurs. The ROR bit cannot
be placed into the FIFO and all data associated with the
frame is lost.
Receive Information Buffer Lost. Set to a “1” when the last
data for a frame is read from the receive FIFO and the
RFC bit is still set from a previous end of frame. This bit is
cleared by writing a “1” to this bit. This is triggered if the
RFC bit is already set before the last data from a frame is
read from the IrData register. It indicates that the data from
the IrRIB register was lost. This can occur if the CPU does
not respond to the RFC interrupt before another (short)
frame completes and is read from the IrData register by
the DMA controller.
Received Frame Complete. Set to “1” when the last data
for a frame is read from the receive FIFO (via the IrData
register). This event also triggers the IrRIB to load the
IrFlag and byte count. This bit is cleared when the IrRIB
register is read.
24
8
RSVD
23
7
RFL
22
6
RIL
21
5
RFC
20
4
RFS
19
3
TAB
18
2
TFC
17
1
DS785UM1
TFS
16
0
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