EP9312-CB Cirrus Logic Inc, EP9312-CB Datasheet - Page 703

• Manufacturer Part Number: EP9312-CB
• Description: System-on-Chip Processor
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-CB

• Peak Reflow Compatible (260 C): No
• A/d Converter: 12 Bits
• Leaded Process Compatible: No
• No. Of I/o Pins: 65
• Package / Case: 352-BGA
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1257

AC97IEx
AC97S1Data
DS785UM1
31
15
31
15
Address:
Definition:
Bit Descriptions:
Address:
Definition:
30
14
30
14
29
13
29
13
28
12
28
12
AC97IE1 - 0x8088_0018 - Read/Write
AC97IE2 - 0x8088_0038 - Read/Write
AC97IE3 - 0x8088_0058 - Read/Write
AC97IE4 - 0x8088_0078 - Read/Write
Interrupt Enable Register. The AC97IE registers control the Interrupt Enables
for the FIFOs within the controller. All bits are cleared on reset.
RSVD:
RIE:
TIE:
RTIE:
TCIE:
0x8088_0080 - Read/Write
Slot 1 Data Register. The AC97S1Data register is a read / write register. When
a write has occurred to this register, the data contained within it is sent on the
RSVD
27
11
27
11
26
10
26
10
RSVD
Copyright 2007 Cirrus Logic
25
25
9
9
Reserved. Unknown During Read.
Receive Interrupt Enable - If this bit is set to “1”, the FIFO
receive interrupt is enabled.
Transmit Interrupt Enable - If this bit is set to “1”, the FIFO
transmit interrupt is enabled.
Receive Timeout Interrupt Enable - If this bit is set to “1”,
the FIFO receive timeout interrupt is enabled.
Transmit Complete Interrupt Enable - If this bit is set to “1”,
the FIFO transmit complete interrupt is enabled.
24
24
8
8
RSVD
RSVD
23
23
7
7
22
22
6
6
21
21
5
5
20
20
4
4
DATA
RIE
19
19
3
3
EP93xx User’s Guide
TIE
18
18
2
2
AC’97 Controller
RTIE
17
17
1
1
22-15
TCIE
16
16
0
0
22