EP9312-CB Cirrus Logic Inc, EP9312-CB Datasheet - Page 348

• Manufacturer Part Number: EP9312-CB
• Description: System-on-Chip Processor
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-CB

• Peak Reflow Compatible (260 C): No
• A/d Converter: 12 Bits
• Leaded Process Compatible: No
• No. Of I/o Pins: 65
• Package / Case: 352-BGA
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1257

9
SelfCtl
9-46
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
RSVD
31
15
Address:
Chip Reset:
Soft Reset:
Definition:
Bit Descriptions:
Note: Clause 22.2.2.1 in the IEEE-802-3 specification states that the maximum MDC clock rate
Note: The user must check the datasheet of the PHY being used in the design. If the PHY needs
30
14
is 2.5 MHz. Most PHYs support clock rates faster than 2.5 MHz. So, modify the MDCDIV
value according to the PHYs specification.
a preamble for reading/writing to/from PHY registers, the PSPRS must be cleared (set to
0).
29
13
28
12
PB:
STxON:
0x8001_0020 - Read/Write
0x0000_0F10
0x0000_0000
Self Control Register
RSVD:
MDCDIV:
PSPRS:
MDCDIV
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Pause Busy: This bit remains set as long as a pause
frame is being transmitted. Only one pause frame may be
sent at any time, therefore the Send Pause and Pause
Busy bits should be zero before a new pause frame is
defined.
Serial Transmit ON. The transmitter is enabled when set.
When clear, no transmissions are allowed. When a frame
is being transmitted, and STxON is cleared, then that
transmit frame is completed. No subsequent frames are
transmitted until STxON is set again.
Reserved. Unknown During Read.
MDC Clock Divisor. HCLK is divided by MDCDIV + 1 to
create the MDC clock frequency. Default value is 0x07,
which is divide by 8.
Preamble Suppress. Default is 1.
1 = The first MDC qualifies an SFD on MDIO.
0 = Get 32 ones before SFD.
PSPRS
24
8
RSVD
RWP
23
7
RSVD
22
6
GPO0
21
5
PUWE
20
4
PDWE
19
3
MIIL
18
2
RSVD
17
1
DS785UM1
RESET
16
0