EP9312-CB Cirrus Logic Inc, EP9312-CB Datasheet - Page 395

• Manufacturer Part Number: EP9312-CB
• Description: System-on-Chip Processor
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-CB

• Peak Reflow Compatible (260 C): No
• A/d Converter: 12 Bits
• Leaded Process Compatible: No
• No. Of I/o Pins: 65
• Package / Case: 352-BGA
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1257

DS785UM1
10.1.1 DMA Features List
10.1 Introduction
The DMA Controller can be used to interface streams from 20 internal peripherals to the
system memory using 10 fully-independent programmable channels that consist of 5 Memory
to Internal Peripheral (M2P) transmit channels and 5 Peripheral to Memory (P2M) receive
channels.
The DMA Controller can also be used to interface streams from Memory to Memory (M2M),
from Memory to Internal Peripheral (M2P), or from Memory to External Peripheral (M2P),
using 2 dedicated M2M channels. External handshake signals are optionally available to
support Memory to/from External Peripheral transfers (M2P/P2M). A software trigger is
available for Memory to Memory transfers, and a hardware trigger is available for Memory to
Internal Peripheral.
On the EP93xx chip the following peripherals may be allocated to the 10 channels.
Each peripheral has it’s own bi-directional DMA bus capable of transferring data in both
directions simultaneously. All memory transfers take place via the main system AHB bus.
SSP and IDE can also use the M2M channels to send or receive data using their memory
mapping to perform transfers.
SSPRx, SSPTx, and IDE have access to DMA M2M hardware transfer requests.
DMA specific features are:
• I
• AAC (which contains 3 Tx and 3 Rx DMA Channels)
• UART1 (which contains 1 Tx and 1 Rx DMA Channels)
• UART2 (which contains 1 Tx and 1 Rx DMA Channels)
• UART3 (which contains 1 Tx and 1 Rx DMA Channels)
• IrDA (which contains 1 Tx and 1 Rx DMA Channels)
• Ten fully independent, programmable DMA controller internal M2P/P2M channels (5 Tx
• Two dedicated channels for Memory-to-Memory (M2M) and Memory-to-External
and 5 Rx).
Peripheral Transfers (external M2P/P2M).
2
S (which contains 3 Tx and 3 Rx DMA Channels)
Copyright 2007 Cirrus Logic
10DMA Controller
Chapter 10
10-1
10