EP9312-CB Cirrus Logic Inc, EP9312-CB Datasheet - Page 791
![System-on-Chip Processor](/photos/12/23/122390/mfg_ep9312_series_sml.jpg)
EP9312-CB
Manufacturer Part Number
EP9312-CB
Description
System-on-Chip Processor
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets
1.EP9307-CRZ.pdf
(824 pages)
2.EP9312-IBZ.pdf
(4 pages)
3.EP9312-CB.pdf
(62 pages)
4.EP9312-CB.pdf
(17 pages)
Specifications of EP9312-CB
Peak Reflow Compatible (260 C)
No
A/d Converter
12 Bits
Leaded Process Compatible
No
No. Of I/o Pins
65
Package / Case
352-BGA
Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Other names
598-1257
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP9312-CB
Manufacturer:
CIRRUS
Quantity:
20 000
- EP9307-CRZ PDF datasheet
- EP9312-IBZ PDF datasheet #2
- EP9312-CB PDF datasheet #3
- EP9312-CB PDF datasheet #4
- Current page: 791 of 824
- Download datasheet (13Mb)
DS785UM1
28.1 Introduction
The General Purpose Input/Output (GPIO) is an Advanced Peripheral Bus (APB) slave
module. The GPIO block is the primary controller for the EGPIO, RDLED, GRLED, SLA[1:0],
EECLK, and EEDAT pins. It is a secondary controller for the ROW[7:0], COL[7:0], PCMCIA
and IDE control pins.
There are two types of GPIOs, standard and enhanced. The enhanced GPIO, called EGPIO,
have interrupt generation capability.
The GPIO block has eight ports, named Port A through Port H. Ports C, D, E, G, and H are
standard GPIO ports. Ports A, B, and F are enhanced GPIO ports.
Each GPIO port controls eight individual pins. Each port has an 8-bit data register and an 8-
bit data direction register. The EGPIO ports each have additional 8-bit registers for interrupt
configuration and status. The control of an individual pin is determined in a bit-slice fashion
across all registers for that port; only a single bit at a particular index from each register
affects or is affected by that pin.
Note: The EP9301 and EP9302 processors each have 18 standard GPIOs and 19 enhanced
Note: The EP9307 processor has 30 standard GPIOs and 18 enhanced GPIOs.
Note: The EP9312 processor has 31 standard GPIOs and 16 enhanced GPIOs.
Note: The EP9315 processor has 31 standard GPIOs and 24 enhanced GPIOs.
GPIOs.
Copyright 2007 Cirrus Logic
28GPIO Interface
Chapter 28
28-1
28
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