EP9312-CB Cirrus Logic Inc, EP9312-CB Datasheet - Page 459
![System-on-Chip Processor](/photos/12/23/122390/mfg_ep9312_series_sml.jpg)
EP9312-CB
Manufacturer Part Number
EP9312-CB
Description
System-on-Chip Processor
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets
1.EP9307-CRZ.pdf
(824 pages)
2.EP9312-IBZ.pdf
(4 pages)
3.EP9312-CB.pdf
(62 pages)
4.EP9312-CB.pdf
(17 pages)
Specifications of EP9312-CB
Peak Reflow Compatible (260 C)
No
A/d Converter
12 Bits
Leaded Process Compatible
No
No. Of I/o Pins
65
Package / Case
352-BGA
Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Other names
598-1257
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP9312-CB
Manufacturer:
CIRRUS
Quantity:
20 000
- EP9307-CRZ PDF datasheet
- EP9312-IBZ PDF datasheet #2
- EP9312-CB PDF datasheet #3
- EP9312-CB PDF datasheet #4
- Current page: 459 of 824
- Download datasheet (13Mb)
HcInterruptDisable
DS785UM1
MIE
31
15
Address:
Default:
Definition:
Bit Descriptions:
OC
30
14
29
13
28
12
FNO:
RHSC:
OC:
MIE:
0x8002_0014
0x0000_0000
Disables interrupt sources.
RSVD:
SO:
WDH:
SF:
RD:
UE:
RSVD
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
FrameNumberOverflow. Enable interrupt generation due
to Frame Number Overflow.
RootHubStatusChange. Enable interrupt generation due to
Root Hub Status Change.
OwnershipChange. Enable interrupt generation due to
Ownership Change.
Master Interrupt Enable. A zero written to this field is
ignored by HC. A one written to this field enables interrupt
generation due to events specified in the other bits of this
register. This is used by HCD as a Master Interrupt
Enable.
Reserved. Unknown During Read.
SchedulingOverrun: Disable interrupt generation due to
Scheduling Overrun.
WritebackDoneHead: Disable interrupt generation due to
HcDoneHead Writeback.
StartofFrame: Disable interrupt generation due to Start of
Frame.
ResumeDetected: Disable interrupt generation due to
Resume Detect.
UnrecoverableError: Disable interrupt generation due to
Unrecoverable Error.
24
8
23
7
RSVD
RHSC
22
6
FNO
21
5
Universal Serial Bus Host Controller
UE
20
4
RD
19
3
EP93xx User’s Guide
SF
18
2
WDH
17
1
11-19
SO
16
0
11
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