EP9312-CB Cirrus Logic Inc, EP9312-CB Datasheet - Page 230
![System-on-Chip Processor](/photos/12/23/122390/mfg_ep9312_series_sml.jpg)
EP9312-CB
Manufacturer Part Number
EP9312-CB
Description
System-on-Chip Processor
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets
1.EP9307-CRZ.pdf
(824 pages)
2.EP9312-IBZ.pdf
(4 pages)
3.EP9312-CB.pdf
(62 pages)
4.EP9312-CB.pdf
(17 pages)
Specifications of EP9312-CB
Peak Reflow Compatible (260 C)
No
A/d Converter
12 Bits
Leaded Process Compatible
No
No. Of I/o Pins
65
Package / Case
352-BGA
Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Other names
598-1257
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP9312-CB
Manufacturer:
CIRRUS
Quantity:
20 000
- EP9307-CRZ PDF datasheet
- EP9312-IBZ PDF datasheet #2
- EP9312-CB PDF datasheet #3
- EP9312-CB PDF datasheet #4
- Current page: 230 of 824
- Download datasheet (13Mb)
7
VLineStep
7-48
Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
31
15
Address: 0x8003_0038
Default: 0x0000_0000
Definition: Video Line Step Size Register
Bit Descriptions:
30
14
RSVD
29
13
28
12
LEN:
RSVD:
STEP:
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Length - Read/Write
The Length value written to this field specifies, in 32-bit
words, the length of video lines that are scanned to the
display. Please see
on page 7-31
The remainder of the last word in a video line may not be
used as long as the blanking time is greater than the
remaining number of pixels. The extra pixels will enter the
video chain, but will exit the pipeline during the blanking
interval. When the end of LEN is reached, STEP in the
VLineStep
Reserved - Unknown during read
Step - Read/Write
When the end of the video line is reached (see LEN in
LineLength
(specified in 32-bit words) is added to the address for
every video line that is scanned to the display. Please see
“Memory Setup Example” on page
This allows the screen width to be smaller than the video
image width in SDRAM.
24
8
RSVD
register is added to the address for video data.
23
7
register), the Step value written to this field
and
22
6
“Memory Setup Example” on page
STEP
“Setting up the LineLength Register”
21
5
20
4
7-31.
19
3
18
2
17
1
DS785UM1
7-31.
16
0
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