UPSD3433EB40U6 STMicroelectronics, UPSD3433EB40U6 Datasheet - Page 53

• Manufacturer Part Number: UPSD3433EB40U6
• Description: MCU 8BIT 8032 128KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3433EB40U6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• For Use With: 497-5518 - EVAL BOARD RFID READER497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-5660

uPSD34xx
Note:
If an interrupt flag is not cleared after servicing the interrupt, an unwanted interrupt will occur
upon exiting the ISR.
After the interrupt is serviced, the last instruction executed by the ISR is RETI. The RETI
informs the MCU that the ISR is no longer in progress and the MCU pops the top two bytes
from the stack and loads them into the PC. Execution of the interrupted program continues
where it left off.
An ISR must end with a RETI instruction, not a RET. An RET will not inform the interrupt
control system that the ISR is complete, leaving the MCU to think the ISR is still in progress,
making future interrupts impossible.
Table 16.
Reserved 0 (high) 0063h
Interrupt
Overflow
Overflow
Overflow
Interrupt
Interrupt
External
External
Timer 0
Timer 1
Timer 2
Source
UART0
or TX2
INT0
INT1
ADC
USB
SPI
Pin
I
2
C
Priority
Polling
Interrupt summary
10
1
2
3
4
5
6
7
8
9
r Addr
000Bh
001Bh
002Bh
003Bh
0003h
0013h
0023h
0053h
0033h
0043h INTR (S1STA.5)
Vecto
TEISF, RORISF,
TF2 (T2CON.7)
Flag Bit Name
(SPISTAT[3:0])
TF0 (TCON.5)
TF1 (TCON.7)
RI (SCON0.0)
IE0 (TCON.1)
TI (SCON0.1)
IE1 (TCON.3
(T2CON.6)
TISF, RISF
(ACON.7)
position)
Interrupt
Pending
(SFR.bit
1 = Intr
0 = No
AINTF
EXF2
–
–
(1)
Hardware?
Edge - Yes
Edge - Yes
Level - No
Level - No
Flag Bit
Cleared
Auto-
Yes
Yes
Yes
Yes
No
No
No
No
by
–
Enable Bit Name
0 = Intr Disabled
1 = Intr Enabled
EUSB (IEA.0)
EADC (IEA.7)
ESPI (IEA.6)
EI
EX0 (IE.0)
ET0 (IE.1)
EX1 (IE.2)
ET1 (IE.3)
ES0 (IE.4)
ET2 (IE.5)
position)
(SFR.bit
2
C (IEA.1)
–
Interrupt system
1= High Priority
0 = Low Priority
PUSB (IPA.0)
PADC (IPA.7)
PSPI (IPA.6)
PI
Priority Bit
PX0 (IP.0)
PT0 (IP.1)
PX1 (IP.2)
PT1 (IP.3)
PS0 (IP.4)
PT2 (IP.5)
position)
(SFR.bit
2
Name
C (IPA.1)
–
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