UPSD3433EB40U6 STMicroelectronics, UPSD3433EB40U6 Datasheet - Page 166

• Manufacturer Part Number: UPSD3433EB40U6
• Description: MCU 8BIT 8032 128KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3433EB40U6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• For Use With: 497-5518 - EVAL BOARD RFID READER497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-5660

USB interface
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Table 83.
Bit
Bit 7
7
6
5
4
3
2
1
–
USB Endpoint Control Register (UCON)
The Endpoint selected by the USB Endpoint Select Register (see
page
Endpoint Control Register (see
to control the selected Endpoint and provides some status about that Endpoint.
TOGGLE
ENABLE
Symbol
STALL
165) determines the direction and FIFO (IN or OUT) that is controlled by the USB
–
–
–
–
Bit 6
USB Endpoint Control Register (UCON 0F1h, Reset Value 08h)
–
R/W
R/W
R/W
R
–
–
–
–
Bit 5
–
Reserved
Reserved
Reserved
Reserved
Selected FIFO Enable Bit.
Note: All FIFOs for each endpoint is enabled after a reset.
Stall Control Bit
When this bit is set, the Endpoint returns a STALL handshake whenever
it receives an IN or OUT token.
Data Toggle Bit
– Endpoint IN Case
The state of this bit determines the type of data packet (0=DATA0 or
1=DATA1) that will be sent during the next IN transaction. This bit is
managed by the USB SIE. It is only toggled when an ACK is properly
received during the IN transaction. In some cases it may be necessary
for firmware to clear this bit. In this case, see the Important Notes
section at the end of this data sheet.
– Endpoint OUT Case
The state of this bit indicates the type of data packet PID that the USB
SIE expects to receive with the next OUT transaction (0=DATA0,
1=DATA1). If the Data Toggle for the next OUT transaction received is
not as expected, the USB SIE assumes the host is retransmitting the
last packet. In this case, an ACK is sent but no interrupt is generated
since the original transmission of the packet was OK. This bit is
managed by the USB SIE. It is only toggled when an OUT packet is
properly received. In some cases it may be necessary for firmware to
clear this bit. In this case, see the Important Notes section at the end of
this data sheet.
Important notes:
1. Disabling and enabling the USB SIE using the USBEN bit the UCTL
register clears the TOGGLE bit for both directions of all endpoints.
2. Revision A silicon: See the Important Notes section at the end of the
data sheet that explains the workaround for clearing this data toggle bit.
3. Revision B silicon: Disabling and Enabling the selected FIFO using
the ENABLE bit in this register clears the data toggle bit for the selected
endpoint's FIFO.
Bit 4
–
Table
83). The USB Endpoint Control Register is used
Enable
Bit 3
Definition
STALL
Bit 2
TOGGLE
Bit 1
Table 82 on
uPSD34xx
Bit 0
BSY