UPSD3433EB40U6 STMicroelectronics, UPSD3433EB40U6 Datasheet - Page 155

• Manufacturer Part Number: UPSD3433EB40U6
• Description: MCU 8BIT 8032 128KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3433EB40U6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• For Use With: 497-5518 - EVAL BOARD RFID READER497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-5660

uPSD34xx
25.4.3
Table 70.
Table 71.
USB interrupts
There are many USB related events that generate an interrupt. The events that generate an
interrupt are selectively enabled through the use of the USB Interrupt Enable Registers. All
USB interrupts are serviced through a single interrupt vector (see
system on page 52
firmware must check the USB Interrupt Flag Registers to determine the source of the
interrupt, clear that interrupt flag and process the interrupt before returning to the interrupted
code.
Bit 7
6:0
Bit
–
7
Bit 7
Bit
–
7
6
5
4
3
2
1
0
USBADDR
Symbol
Bit 6
USB device address register (UADDR 0E2h, reset value 00h)
Pairing control register (UPAIR 0E3h, reset value 00h)
PR3OUT
PR1OUT
–
Symbol
PR3IN
PR1IN
Bit 6
–
–
–
–
–
for the address of the interrupt vector). When a USB interrupt occurs,
Bit 5
R/W
R/W
–
Bit 5
R/W
R/W
R/W
R/W
R/W
–
–
–
–
–
Reserved
USB Address of the device.
These bits are cleared with a Hardware RESET. When a USB
RESET is detected, the address register should be cleared.
Reserved
Reserved
Reserved
Reserved
Setting this bit enables double buffering of the OUT FIFOs for
Endpoints 3 and 4. Access to the double buffered FIFOs is
through Endpoint3’s OUT FIFO.
Setting this bit enables double buffering of the OUT FIFOs for
Endpoints 1 and 2. Access to the double buffered FIFOs is
through Endpoint1’s OUT FIFO.
Setting this bit enables double buffering of the IN FIFOs for
Endpoints 3 and 4. Access to the double buffered FIFOs is
through Endpoint3’s IN FIFO.
Setting this bit enables double buffering of the IN FIFOs for
Endpoints 1 and 2. Access to the double buffered FIFOs is
through Endpoint1’s IN FIFO.
Bit 4
Bit 4
–
USBADDR[6:0]
PR3OUT
Bit 3
Bit 3
Definition
Definition
PR1OUT
Bit 2
Bit 2
Section 13: Interrupt
Bit 1
PR3IN
Bit 1
USB interface
PR1IN
Bit 0
Bit 0
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