UPSD3433EB40U6 STMicroelectronics, UPSD3433EB40U6 Datasheet - Page 162

• Manufacturer Part Number: UPSD3433EB40U6
• Description: MCU 8BIT 8032 128KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3433EB40U6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• For Use With: 497-5518 - EVAL BOARD RFID READER497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-5660

USB interface
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Table 79.
Bit 7
Bit
USB IN FIFO NAK Interrupt Flag (UIF3)
The USB IN FIFO NAK Interrupt Flag register (see
indicate when an IN Endpoint FIFO is not ready. The Endpoint FIFO is not ready when
data has not been loaded into its FIFO and the USIZE register has not been written to
(writing to the USIZE register puts the FIFO in a “ready” to send data state). Until the
FIFO is ready, the SIE will continue to NAK all IN requests to the respective Endpoint.
Once set, firmware must clear the flag by writing a '0' to the appropriate bit. When
FIFOs are paired, only the odd numbered FIFO Interrupt Flags are active.
–
7
6
5
4
3
2
1
0
USB IN FIFO NAK interrupt flag (UIF3 0EBh, reset value 00h)
Symbol
NAK4F
NAK3F
NAK2F
NAK1F
NAK0F
Bit 6
–
–
–
–
Bit 5
R/W
R/W
R/W
R/W
R/W
R/W
–
–
–
–
Reserved
Reserved
Reserved
Endpoint 4 IN FIFO NAK Interrupt flag
This bit is set when the SIE responded to an IN request with a
NAK since the FIFO was not ready.
Endpoint 3 IN FIFO NAK Interrupt flag
This bit is set when the SIE responded to an IN request with a
NAK since the FIFO was not ready.
Endpoint 2 IN FIFO NAK Interrupt flag
This bit is set when the SIE responded to an IN request with a
NAK since the FIFO was not ready.
Endpoint 1 IN FIFO NAK Interrupt flag
This bit is set when the SIE responded to an IN request with a
NAK since the FIFO was not ready.
Endpoint 0 IN FIFO NAK Interrupt flag
This bit is set when the SIE responded to an IN request with a
NAK since the FIFO was not ready.
NAK4F
Bit 4
NAK3F
Bit 3
Table
Definition
NAK2F
Bit 2
79) contains flags that
NAK1F
Bit 1
uPSD34xx
NAK0F
Bit 0