UPSD3433EB40U6 STMicroelectronics, UPSD3433EB40U6 Datasheet - Page 42

• Manufacturer Part Number: UPSD3433EB40U6
• Description: MCU 8BIT 8032 128KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3433EB40U6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• For Use With: 497-5518 - EVAL BOARD RFID READER497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-5660

uPSD34xx instruction set summary
10
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uPSD34xx instruction set summary
Tables
number of bytes and number of machine cycles required to implement each instruction. This
is the standard 8051 instruction set.
The meaning of “machine cycles” is how many 8032 MCU core machine cycles are required
to execute the instruction. The “native” duration of all machine cycles is set by the memory
wait state settings in the SFR, BUSCON, and the MCU clock divider selections in the SFR,
CCON0 (i.e. a machine cycle is typically set to 4 MCU clocks for a 5V uPSD34xx). However,
an individual machine cycle may grow in duration when either of two things happen:
1.
2.
See
But generally speaking, during typical program execution, the PFQ is not empty and the BC
has no misses, producing very good performance without extending the duration of any
machine cycles.
Table 6.
ADD
ADD
ADD
ADD
ADDC
ADDC
ADDC
ADDC
SUBB
SUBB
SUBB
SUBB
INC
INC
INC
INC
DEC
DEC
DEC
DEC
Mnemonic
Section 5: 8032 MCU core performance enhancements on page 23
a stall is imposed while loading the 8032 Pre-Fetch Queue (PFQ); or
the occurrence of a cache miss in the Branch Cache (BC) during a branch in program
execution flow.
6
through
Arithmetic instruction set
(1)
A, Rn
A, Direct
A, @Ri
A, #data
A, Rn
A, direct
A, @Ri
A, #data
A, Rn
A, direct
A, @Ri
A, #data
A
Rn
direct
@Ri
A
Rn
direct
@Ri
and Use
11
list all of the instructions supported by the uPSD34xx, including the
Add register to ACC
Add direct byte to ACC
Add indirect SRAM to ACC
Add immediate data to ACC
Add register to ACC with carry
Add direct byte to ACC with carry
Add indirect SRAM to ACC with carry
Add immediate data to ACC with carry
Subtract register from ACC with borrow
Subtract direct byte from ACC with borrow
Subtract indirect SRAM from ACC with borrow
Subtract immediate data from ACC with borrow
Increment A
Increment register
Increment direct byte
Increment indirect SRAM
Decrement ACC
Decrement register
Decrement direct byte
Decrement indirect SRAM
Description
or more details.
Length/Cycles
1 byte/1 cycle
1 byte/1 cycle
1 byte/1 cycle
1 byte/1 cycle
2 byte/1 cycle
1 byte/1 cycle
2 byte/1 cycle
1 byte/1 cycle
2 byte/1 cycle
1 byte/1 cycle
2 byte/1 cycle
2 byte/1 cycle
1 byte/1 cycle
2 byte/1 cycle
1 byte/1 cycle
2 byte/1 cycle
1 byte/1 cycle
1 byte/1 cycle
1 byte/1 cycle
2 byte/1 cycle
uPSD34xx