UPSD3433EB40U6 STMicroelectronics, UPSD3433EB40U6 Datasheet - Page 232

• Manufacturer Part Number: UPSD3433EB40U6
• Description: MCU 8BIT 8032 128KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3433EB40U6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• For Use With: 497-5518 - EVAL BOARD RFID READER497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-5660

PSD module
28.5.39
Note:
232/293
1
2
3
Figure 83. Using the Design Assistant in PSDsoft Express for Simple PLD Example
Latched address output mode
In the MCU Module, the data bus Bits D0-D15 are multiplexed with the address Bits A0-A15,
and the ALE signal is used to separate them with respect to time. Sometimes it is necessary
to send de-multiplexed address signals to external peripherals or memory devices. Latched
Address Output mode will drive individual demuxed address signals on pins of Ports A or B.
Port pins can be designated for this function on a pin-by-pin basis, meaning that an entire
port will not be sacrificed if only a few address signals are needed.
To activate this mode, the desired pins on Port A or Port B are designated as “Latched
Address Out” in PSDsoft. Then in the 8032 initialization firmware, a logic ’1’ is written to the
csiop Control register for Port A or Port B in each bit position that corresponds to the pin of
the port driving an address signal.
locations and bit assignments.
The latched low address byte A4-A7 is available on both Port A and Port B. The high
address byte A8-A15 is available on Port B only. Selection of high or low address byte is
specified in PSDsoft Express.
Table 134. Latched address output, port A contro register
Port A not available on 52-pin uPSD34xx devices
For each bit, 1 = drive demuxed 8032 address signal on pin, 0 = pin is default mode, MCU
I/O
Default state for register is 00h after reset or power-up
(addr A7)
Bit 7
PA7
offset 02h)l
(addr A6)
Bit 6
PA6
(addr A5)
Bit 5
PA5
Table 134
(addr A4)
Bit 4
PA4
and
(addr A3)
Table 135
Bit 3
PA3
define the csiop Control register
(Addr A2)
Bit 2
PA2
(1)
(address = csiop +
(addr A1)
Bit 1
PA1
uPSD34xx
(addr A0)
Bit 0
PA0