UPSD3433EB40U6 STMicroelectronics, UPSD3433EB40U6 Datasheet - Page 244

• Manufacturer Part Number: UPSD3433EB40U6
• Description: MCU 8BIT 8032 128KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3433EB40U6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• For Use With: 497-5518 - EVAL BOARD RFID READER497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-5660

PSD module
Note:
Note:
Note:
244/293
1
Table 145. Power management mode register PMMR2 (address = csiop + offset B4h)
The bits of this register are cleared to zero following Power-up. Subsequent Reset (RST)
pulses do not clear the registers.
Blocking bits should be set to logic ’1’ only if the signal is not needed in a DPLD or GPLD
logic equation.
Table 146. Power Management Mode Register PMMR3 (address = csiop + offset C7h)
The bits of this register are cleared to zero following Power-up. Subsequent Reset (RST)
pulses do not clear the registers.
Bit 3-
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 5
Bit 7
Bit 0
Bit 1 FORCE_PD
7
Blocking Bit,
Blocking Bit,
Blocking Bit,
Blocking Bit,
Blocking Bit,
PSEN to
PLDs
PLDs
PLDs
PLDs
PLDs
PC7 to
ALE to
WR to
RD to
X
X
X
X
X
(1)
(1)
(1)
(1)
(1)
0 =
1 =
0 =
1 =
0 =
1 =
0 =
1 =
0 =
1 =
0 =
1 =
on
off
on
off
on
off
on
off
on
off
off
on
0
0
0
0
0
Not used, and should be set to zero.
Not used, and should be set to zero.
8032 WR input to the PLD Input Bus is not blocked.
8032 WR input to PLD Input Bus is blocked, saving power.
8032 RD input to the PLD Input Bus is not blocked.
8032 RD input to PLD Input Bus is blocked, saving power.
8032 PSEN input to the PLD Input Bus is not blocked.
8032 PSEN input to PLD Input Bus is blocked, saving power.
8032 ALE input to the PLD Input Bus is not blocked.
8032 ALE input to PLD Input Bus is blocked, saving power.
Pin PC7 input to the PLD Input Bus is not blocked.
Pin PC7 input to PLD Input Bus is blocked, saving power.
Not used, and should be set to zero.
Not used, and should be set to zero.
APD counter will cause Power-Down Mode if APD is enabled.
Power-Down mode will be entered immediately regardless of APD
activity.
Not used, and should be set to zero.
uPSD34xx