UPSD3433EB40U6 STMicroelectronics, UPSD3433EB40U6 Datasheet - Page 226

MCU 8BIT 8032 128KB FLASH 80TQFP

UPSD3433EB40U6

Manufacturer Part Number
UPSD3433EB40U6
Description
MCU 8BIT 8032 128KB FLASH 80TQFP
Manufacturer
STMicroelectronics
Series
µPSDr
Datasheet

Specifications of UPSD3433EB40U6

Core Processor
8032
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, IrDA, SPI, UART/USART, USB
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
46
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TQFP, 80-VQFP
For Use With
497-5518 - EVAL BOARD RFID READER497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
497-5660

Available stocks

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Quantity
Price
Part Number:
UPSD3433EB40U6
Manufacturer:
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Quantity:
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Part Number:
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PSD module
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following sections. Some operating modes can be defined using PSDsoft Express, and
some by the 8032 writing to the csiop registers at run-time, and some require both. For
example, PLD I/O, Latched Address Out, and Peripheral I/O modes must be defined in
PSDsoft Express and programmed into the device using JTAG, but an additional step must
happen at run-time to activate Latched Address Out mode and Peripheral I/O mode, but not
needed for PLD I/O. In another example, MCU I/O mode is controlled completely by the
8032 at run-time and only a simple pin name declaration is needed in PSDsoft Express for
documentation.
Table 116 on page 223
actions are required by the 8032 at run-time to achieve the various port functions.
Figure 80. Detail of a single I/O port (typical of ports A, B, C)
Table 120. Port operating modes
MCU I/O
PLD I/O
OMC MCELLAB Outputs
OMC MCELLBC Outputs
External Chip-Select
Outputs
PLD Inputs
FROM AND-OR ARRAY
FROM PLD INPUT BUS
Port Operating Mode
ALLOCATOR
FROM OMC
LATCHED ADDR BIT, PORT A or B
DATA
8032
BITS
8032
DATA
8032 RD
FROM OMC OUTPUT
8032
D BIT, PERIPH I/O MODE, Port A
PSD MODULE RESET
WR
PT OUTPUT ENABLE (.OE)
BIT
summarizes what actions are needed in PSDsoft Express and what
D
REGIS-
CSIOP
TERS
Port A (80-pin
CLR
M
P
D
B
U
X
Q
Q
Q
Q
1
2
3
4
5
6
REGISTERS
DIRECTION
DRIVE
CONTROL
DATA OUT
RESET
(MCUI/O)
ONE of 6
only)
CSIOP
DIRECTION
DRIVE SELECT
CONTROL
DATA OUT (MCUI/O)
ENABLE OUT
DATA IN (MCUI/O)
Yes
Yes
Yes
No
No
Port B
Yes
Yes
Yes
Yes
No
PSDsoft
OUTPUT
SELECT
1
2
3
4
M
O
U
T
P
U
T
U
X
PERIPH I/O
DATA BIT
Port C
MUX
Yes
OE
Yes
Yes
No
No
WR
(1)
PERIPHERAL I/O
(PORT A ONLY)
MODE SETS
DIRECTION
RD PIO EN
TO IMC
Port D
OUTPUT ENABLE
Yes
Yes
Yes
No
No
PSELx
DRIVE TYPE
OUTPUT
DRIVER
MCU I/O mode on
BUFFER
PLD I/O mode on
INPUT
I/O PORT
LOGIC
page 228
page 230
Find it
uPSD34xx
PORT A, B, C
AI07873A
TYPICAL
PIN

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