UPSD3433EB40U6 STMicroelectronics, UPSD3433EB40U6 Datasheet - Page 154

• Manufacturer Part Number: UPSD3433EB40U6
• Description: MCU 8BIT 8032 128KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3433EB40U6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• For Use With: 497-5518 - EVAL BOARD RFID READER497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-5660

USB interface
Note:
25.4.1
25.4.2
154/293
Bits marked with a “–“ are Reserved.
USB device address register
Initially when a device is connected to the USB, it responds to the host on address 0. Using
the Set_Address request, the host assigns a unique address to the device. The firmware
writes this address to the USB Device Address register (see
the SIE only responds to transactions on that assigned address. This assigned address is in
effect until the device or an upstream hub is disconnected from the USB, the host issues a
USB Reset, or the host shuts down. The address register is cleared with a Hardware
RESET. When a USB RESET is detected, the address register should be cleared.
Endpoint FIFO pairing
Endpoint FIFOs can be paired for double buffering to provide an efficient method for bulk
data transfers. With double buffering enabled, the MCU can operate on one data packet
while another is being transferred over USB.
When two FIFOs are paired, the active FIFO is automatically toggled by the update of
USIZE. The MCU must only use the odd numbered endpoint FIFO when paired in order to
access the active FIFO. For example, if endpoints 3 and 4 OUT FIFOs are paired, the active
FIFO is accessed via endpoint 3’s OUT FIFO (see
(hex)
Addr
SFR
EC
ED
EB
EE
EF
F1
F2
F3
F4
F5
F6
UBASEH
UBASEL
Name
UCON
USIZE
USCV
SFR
UCTL
USEL
USTA
USCI
UIF3
BASEADDR
DIR
7
–
–
–
–
–
–
[7:6]
6
–
–
–
–
–
–
5
–
–
–
–
–
0
–
Bit Name and <Bit Address>
NAK4F
4
–
–
–
–
0
–
BASEADDR[15:8]
RESERVED
ENABLE
USCV[7:0]
NAK3F
RCVT
3
–
–
0
–
SIZE[6:0]
USBEN
NAK2F
SETUP
STALL
2
0
Table
USCI[2:0]
71).
VISIBLE
EP[2:0]
TOGGL
NAK1F
IN
1
E
0
Table
WAKEUP
NAK0F
OUT
BSY
70), and subsequently
0
0
Reset
Value
(hex)
00
00
00
00
08
00
00
00
00
00
uPSD34xx
USB Endpoint
USB Endpoint
Comment
USB IN FIFO
NAK Int. Flag
Address High
Address Low
USB Control
USB Status
USB Setup
USB Setup
USB FIFO
USB Base
USB Base
Command
Command
Valid Size
Control
Select
Index
Value