UPSD3433EB40U6 STMicroelectronics, UPSD3433EB40U6 Datasheet - Page 150

• Manufacturer Part Number: UPSD3433EB40U6
• Description: MCU 8BIT 8032 128KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3433EB40U6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• For Use With: 497-5518 - EVAL BOARD RFID READER497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-5660

USB interface
25.3.3
Note:
150/293
Table 68.
FIFO pairing
The FIFOs on endpoints 1 through 4 may be used independently as shown in
FIFOs with no Pairing or they may be selectively paired to provide double buffering (see
Figure 55 on page
rates with bulk transfers. Double buffering allows the CPU to process a data packet for an
Endpoint while the SIE is receiving or transmitting another packet of data on the same
Endpoint and direction. FIFO pairing is controlled by the USB Pairing Control Register (see
UPAIR,
●
●
●
●
When the FIFOs are paired, the CPU must access the odd numbered FIFO while the even
numbered FIFOs are no longer available for use. Also when they are paired, the active FIFO
is automatically toggled by the update of USIZE.
●
Endpoint
IN FIFO 1 and 2
OUT FIFO 1 and 2
IN FIFO 3 and 4
OUT FIFO 3 and 4
Non-pairing FIFOs Example
Consider a case where the device needs to send 1024 bytes of data to the host.
Without FIFO pairing (see
bytes of data and waits until the host sends an IN token to Endpoint0, and the SIE
transfers the data to the host. Once all 64 bytes have been transferred by the SIE, the
FIFO becomes empty and the CPU starts writing the next 64 bytes of data to the FIFO.
While the CPU is writing the data to the FIFO, the host is sending IN tokens to
Endpoint0, requesting the next 64 bytes of data, but only gets NAKs while the FIFO is
being loaded. Once the FIFO has been loaded by the CPU, the SIE starts sending the
data to the host with the next IN Endpoint0 token. Again, the CPU waits until the SIE
transfers the 64 bytes of data to the host. This is repeated until all 1024 bytes have
been transferred.
0
0
1
1
2
2
3
3
4
4
Table 71 on page
Control
Control
Bulk/Interrupt OUT
Bulk/Interrupt IN
Bulk/Interrupt OUT
Bulk/Interrupt IN
Bulk/Interrupt OUT
Bulk/Interrupt IN
Bulk/Interrupt OUT
Bulk/Interrupt In
uPSD34xx supported endpoints
152). Double buffering provides an efficient way to optimize data transfer
Function
155). FIFO pairing options are listed below:
Figure
54), the CPU loads the IN Endpoint0 FIFO with 64
Max packet size
(FIFO size)
64 Bytes
64 Bytes
64 Bytes
64 Bytes
64 Bytes
64 Bytes
64 Bytes
64 Bytes
64 Bytes
64 Bytes
Supported directions
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
Figure 54
uPSD34xx
as