UPSD3433EB40U6 STMicroelectronics, UPSD3433EB40U6 Datasheet - Page 227

• Manufacturer Part Number: UPSD3433EB40U6
• Description: MCU 8BIT 8032 128KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3433EB40U6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• For Use With: 497-5518 - EVAL BOARD RFID READER497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-5660

uPSD34xx
Note:
2
1
MCELLBC outputs available only on pins PC2, PC3, PC4, and PC7.
JTAG pins (PC0/TMS, PC1/TCK, PC5/TDI, PC6/TDO) are dedicated to JTAG pin functions
(cannot be used for general I/O).
Table 121. Port Configuration Setting Requirements
Latched Address Output
Peripheral I/O Mode
JTAG ISP
4-PIN JTAG ISP
6-PIN JTAG ISP
Address Output
Peripheral I/O
programming)
Port Operating Mode
Operating
MCU I/O
PLD I/O
Latched
(faster
Mode
Port
Choose the MCU I/O
function and declare
the pin name
Choose the PLD
function type, declare
pin name, and specify
logic equation(s)
Choose Latched
Address Out function,
declare pin name
Choose Peripheral
I/O mode function
and specify address
range in DPLD for
PSELx
No action required in
PSDsoft to get 4-pin
JTAG. By default
TDO, TDI, TCK, TMS
are dedicated JTAG
functions.
Choose JTAG TSTAT
function for pin PC3
and JTAG TERR
function for pin PC4.
PSDsoft Express to
Configure each Pin
Required Action in
Port A (80-pin
only)
Yes
Yes
No
Logic '0' (default)
N/A
Logic '1'
N/A
N/A
N/A
Control Register
Value that 8032
writes to csiop
at run-time
Port B
Yes
No
No
Port C
Yes
No
No
Logic 1 = Out of
uPSD
Logic 0 = Into
uPSD
Direction register
has no effect on a
pin if pin is driven
from OMC output
Logic '1' Only
N/A
N/A
N/A
(2)
Register at run-
Value that 8032
writes to csiop
Direction
time
Port D
No
No
No
Peripheral I/O mode
JTAG ISP mode on
Latched address
N/A
N/A
N/A
PIO_EN Bit = Logic
1
(default is '0')
N/A
N/A
(PIO_EN) of csiop
output mode on
Value that 8032
on page 233
VM Register at
writes to Bit 7
page 232
page 234
Find it
run-time
PSD module
227/293