UPSD3433EB40U6 STMicroelectronics, UPSD3433EB40U6 Datasheet - Page 258
UPSD3433EB40U6
Manufacturer Part Number
UPSD3433EB40U6
Description
MCU 8BIT 8032 128KB FLASH 80TQFP
Manufacturer
STMicroelectronics
Series
µPSDr
Datasheet
1.UPSD3434EB40T6.pdf
(293 pages)
Specifications of UPSD3433EB40U6
Core Processor
8032
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, IrDA, SPI, UART/USART, USB
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
46
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TQFP, 80-VQFP
For Use With
497-5518 - EVAL BOARD RFID READER497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
497-5660
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPSD3433EB40U6
Manufacturer:
STMicroelectronics
Quantity:
10 000
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PSD module
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JTAG security setting
A programmable security bit in the PSD Module protects its contents from unauthorized
viewing and copying. The security bit is set by clicking on the “Additional PSD Settings” box
in the main flow diagram of PSDsoft Express, then choosing to set the security bit. Once a
file with this setting is programmed into a uPSD34xx using JTAG ISP, any further attempts to
communicate with the uPSD34xx using JTAG will be limited. Once secured, the only JTAG
operation allowed is a full-chip erase. No reading or modifying Flash memory or PLD logic is
allowed. Debugging operations to the MCU Module are also not allowed. The only way to
defeat the security bit is to perform a JTAG ISP full-chip erase operation, after which the
device is blank and may be used again. The 8032 on the MCU Module will always have
access to PSM Module memory contents through the 8-bit 8032 data bus connecting the
two die, even while the security bit is set.
Initial delivery state
When delivered from STMicroelectronics, uPSD34xx devices are erased, meaning all Flash
memory and PLD configuration bits are logic '1.' Firmware and PLD logic configuration must
be programmed at least the first time using JTAG ISP. Subsequent programming of Flash
memory may be performed using JTAG ISP, JTAG debugging, or the 8032 may run firmware
to program Flash memory (IAP).
uPSD34xx
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