UPSD3433EB40U6 STMicroelectronics, UPSD3433EB40U6 Datasheet - Page 246

• Manufacturer Part Number: UPSD3433EB40U6
• Description: MCU 8BIT 8032 128KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3433EB40U6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• For Use With: 497-5518 - EVAL BOARD RFID READER497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-5660

PSD module
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Forced power-down (FDP)
An alternative to APD is FPD. The resulting power-savings is the same, but the PDN signal
in
firmware sets the FORCE_PD Bit to logic '1' in the csiop Register PMMR3 (Bit 1). FPD will
override APD counter activity when FORCE_PD is set. No external clock source for the APD
counter is needed. The FORCE_PD Bit is cleared only by a reset condition.
Caution must be used when implementing FPD because code memory goes off-line as
soon as PSD Module Power-Down mode is entered, leaving the MCU with no instruction
stream to execute.
The MCU Module must put itself into Power-Down mode after it puts the PSD Module into
Power-Down Mode. How can it do this if code memory goes off-line? The answer is the Pre-
Fetch Queue (PFQ) in the MCU Module. By using the instruction scheme shown in the 8051
assembly code example in
command the MCU Module to Power Down mode after the PDS Module goes to Power-
Down mode. In this case, even though the code memory goes off-line in the PSD Module,
the last few MCU instruction are sourced from the PFQ.
Table 147. Forced power-down example
PDOWN:
LOOP:
Figure 89 on page 247
ANL
ORL
MOV
CLR
JMP
NOP
MOVX
MOV
MOV
JMP
is set and Power-Down mode is entered immediately when
Table
9Dh, #C0h
DPTR, #xxC7
A
LOOP
@DPTR, A
87h, A
A, #02h
LOOP
A8h, #7Fh
147, the PFQ will be loaded with the final instructions to
; disable all interrupts
; ensure PFQ and BC are enabled
; load XDATA pointer to select PMMR3 register (xx
= base
; address of csiop registers)
; clear A
; first loop - fill PFQ/BQ with Power Down
instructions
; second loop - fetch code from PFQ/BC and set
Power-
; Down bits for PSD Module and then MCU
Module
; set FORCE_PD Bit in PMMR3 in PSD Module in
second
; loop
; set PD Bit in PCON Register in MCU Module in
second
; loop
; set power-down bit in the A Register, but not in
PMMR3 or
; PCON yet in first loop
; uPSD enters into Power-Down mode in second
loop
uPSD34xx