UPSD3433EB40U6 STMicroelectronics, UPSD3433EB40U6 Datasheet - Page 274

• Manufacturer Part Number: UPSD3433EB40U6
• Description: MCU 8BIT 8032 128KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3433EB40U6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• For Use With: 497-5518 - EVAL BOARD RFID READER497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-5660

DC and AC parameters
Note:
Note:
274/293
1
2
1
2
Table 167. CPLD macrocell synchronous clock mode timing (5V PSD module)
Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by
given amount.
CLKIN (PD1) t
Table 168. CPLD Macrocell Synchronous Clock Mode Timing (3V PSD Module)
Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by
given amount.
CLKIN (PD1) t
Symbol
Symbol
f
t
t
f
t
t
t
MAX
t
ARD
t
t
MIN
MAX
t
ARD
t
CH
CO
MIN
t
t
CL
CO
t
t
CH
CL
H
S
H
S
Maximum Frequency
External Feedback
Maximum Frequency
Internal Feedback (f
Maximum Frequency
Pipelined Data
Input Setup Time
Input Hold Time
Clock High Time
Clock Low Time
Clock to Output Delay
CPLD Array Delay
Minimum Clock Period
Maximum Frequency
External Feedback
Maximum Frequency
Internal Feedback (f
Maximum Frequency
Pipelined Data
Input Setup Time
Input Hold Time
Clock High Time
Clock Low Time
Clock to Output Delay
CPLD Array Delay
Minimum Clock Period
CLCL
CLCL
Parameter
Parameter
= t
= t
CH
CH
+ t
+ t
CNT
CL
CL
CNT
(2)
.
.
(2)
)
)
Any macrocell
1/(t
Conditions
Conditions
Clock Input
Clock Input
Clock Input
Clock Input
Clock Input
Clock Input
1/(t
1/(t
1/(t
1/(t
macrocell
1/(t
t
t
S
CH
CH
+t
CH
CH
S
Any
S
10)
S
+t
+t
+t
+t
+t
CO
+t
+t
CO
CL
CO
CO
CL
CL
–10)
CL
–
)
)
)
)
Min
Min
12
12
20
15
10
25
0
6
6
0
Max
23.2
30.3
40.0
Max
40.0
66.6
83.3
23
20
13
11
Aloc
Aloc
+ 4
+ 4
+ 2
+ 2
PT
PT
Turbo
Turbo
+ 15
Off
+ 10
Off
rate
Slew
– 6
rate
Slew
– 2
uPSD34xx
(1)
(1)
MHz
MHz
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
Unit
ns
ns
ns
ns
ns
ns
ns