AT91RM9200-CI-002 Atmel, AT91RM9200-CI-002 Datasheet - Page 687

• Manufacturer Part Number: AT91RM9200-CI-002
• Description: IC ARM9 MCU 256 BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-CI-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

Version C
(Note: Page numbers listed below do not correspond to the page numbers as they appear in the revised datasheet format.)
1768I–ATARM–09-Jul-09
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Page 311(GLobal)
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Publication Date: 11-Feb-05
Version C Changes Since Last Issue
All reference to Fast Forcing removed.
Peripheral Data Controller (PDC) changed to Peripheral DMA Controller (PDC)
SmartMedia. NAND Flash coupled to all references to SmartMedia, to read as; NAND Flash/SmartMedia.
Input voltage range for VDDIOM and VDDIOP is 3.0. CSR 05-012
Features: USART Hardware Handshaking. Reference to Software Handshaking removed. CSR 04-066
Figure 1: NWAIT pin added to block diagram. CSR 03-209
Table 1: AT91RM9200 Pinout for 208-lead PQFP package, pins 28, 30, 37 and 39 names modified. CSR 03-
244
Table 7: Pin Description, ICE and JTAG description, “Internal Pullup” added to comments for all signals, except
TDO. CSR 04-315
Table 7: Pin Description, NWAIT pin added. CSR 03-209
Figure 14: AMP Mictor Connector Orientation, correct illustration inserted. CSR 03-242
Table 21: DataFlash Device, AT45DB2562 removed. CSR 03-221
Figure 20: Serial DataFlash Download, Correct illustration inserted. CSR 04-404
Internal Memory Area 0 and Table 35: 16-bit value given to Memory Area 0.
Boot Mode Select: 16-bit value given to external boot memory. CSR 03-205
Table 37: I/O Lines Description NWAIT signal relocated to SMC. CSR 03-209
Table 39: EBI Pins and External Device Connections, Pin/Controller line A13 - A15 changed to A13-A14 and
SDRAMC changed to A11- A12. Pin/Controller line A15 added. CSR 03-217
SMC Chip Select Registers; figures cross-referenced to RWHOLD signal.
EBI_CFGR Register: Warning added to bit #1. CSR 03-243
Table 57: Register Mapping. PERIPH_PTSR offset changed to 0x124. CSR 04-188
SRCTYPE Interrupt source type descriptions changed.
Figure 119. Typical Slow Clock Oscillator Connection; GNDPLL changed to GNDOSC.
Figure 121. Typical Crystal Connection; GNDPLL changed to GNDOSC.
Main Oscillator Control: sentence corrected to read; “....counting down on Slow Clock from the OSCOUNT
value. CSR 03-232
Main Oscillator Bypass: XIN pin information changed. CSR 04-405
PMC Clock Generator PLL A Register; Line added to CKGR_PLLA limitations. CSR 05-005
PMC Clock Generator PLL B Register; Line added to CKGR_PLLB limitations. CSR 05-005
Table 62: Register Mapping. ST_IMR Register is read-only. CSR 03-232
Real Time Controller changed to Real Time Clock. CSR 04-020
Debug Unit (DBGU), ICE Access Prevention removed.
Debut Unit User Interface: Force NTRST Register removed.
PIO. Pull-up Resistor Control. Value of resistor changed from approximately 100 kΩ to 10 kΩ .
PIO. Change PIO_PDSR from Peripheral Data Status Register to Pin Data Status Register
AT91RM9200
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