AT91RM9200-CI-002 Atmel, AT91RM9200-CI-002 Datasheet - Page 164

• Manufacturer Part Number: AT91RM9200-CI-002
• Description: IC ARM9 MCU 256 BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-CI-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

Figure 18-13. One Standard Wait State Access
18.6.4.2
164
AT91RM9200
External Wait States
Notes:
The NWAIT input pin is used to insert wait states beyond the maximum standard wait states pro-
grammable or in addition to. If NWAIT is asserted low, then the SMC adds a wait state and no
changes are made to the output signals, the internal counters or the state. When NWAIT is de-
asserted, the SMC completes the access sequence.
WARNING: Asserting NWAIT low stops the core’s clock and thus stops program execution.
The input of the NWAIT signal is an asynchronous input. To avoid any metastability problems,
NWAIT is synchronized before using it. This operation results in a two-cycle delay.
NWS must be programmed as a function of synchronization time and delay between NWAIT fall-
ing and control signals falling (NRD/NWE), otherwise SMC will not function correctly.
Note:
WARNING: If NWAIT is asserted during a setup or hold timing, the SMC does not function
correctly.
NWS
A[22:0]
NWE
1. Early Read Protocol
2. Standard Read Protocol
Where external NWAIT synchronization is equal to 2 cycles.
The minimum value for NWS if NWAIT is used, is 3.
MCK
NCS
NRD
≥
Wait Delay from nrd/nwe
(1)
1 Wait State Access
(2)
+
external_nwait Synchronization Delay
1768I–ATARM–09-Jul-09
+
1