AT91RM9200-CI-002 Atmel, AT91RM9200-CI-002 Datasheet - Page 202

• Manufacturer Part Number: AT91RM9200-CI-002
• Description: IC ARM9 MCU 256 BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-CI-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

19.6.4
Figure 19-6. Refresh Cycle Followed by a Read Access
202
A[12:0]
D[31:0]
SDWE
(input)
SDCS
SDCK
RAS
CAS
Row n
col c col d
AT91RM9200
SDRAM Controller Refresh Cycles
Dnb
Dnc
Dnd
An auto-refresh command is used to refresh the SDRAM device. Refresh addresses are gener-
ated internally by the SDRAM device and incremented after each auto-refresh automatically.
The SDRAM Controller generates these auto-refresh commands periodically. A timer is loaded
with the value in the register SDRAMC_TR that indicates the number of clock cycles between
refresh cycles.
A refresh error interrupt is generated when the previous auto-refresh command did not perform.
It will be acknowledged by reading the Interrupt Status Register (SDRAMC_ISR).
When the SDRAM Controller initiates a refresh of the SDRAM device, internal memory accesses
are not delayed. However, if the CPU tries to access the SDRAM, the slave will indicate that the
device is busy and the ARM BWAIT signal will be asserted. See
t
RP
= 3
t
RC
= 8
Row m
Figure 19-6
t
RCD
= 3
col a
below.
1768I–ATARM–09-Jul-09
CAS = 2
Dma